• JSTS:Journal of Semiconductor Technology and Science
• /
• v.4 no.2
• /
• pp.110-116
• /
• 2004

We propose a novel sensing scheme, which operates by sensing the difference in voltage between a memory cell and a reference cell for a magneto-resistive random access memory (MRAM). A new midpoint-reference generation circuit is adopted for the reference cell to improve the sensing margin and to guarantee correct operation of sensing circuit for wide range of tunnel magneto resistance (TMR) voltages. In this scheme, the output voltage of the reference cell becomes nearly the midpoint between the cell voltages of high and low states even if the voltage across the magnetic tunnel junction (MTJ) varies.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.46 no.3
• /
• pp.68-74
• /
• 2009

In this paper, we propose an effective memory reduction algorithm to reduce the amount of reference frame buffer and memory bandwidth in video encoder and decoder. In general video codecs, decoded previous frames should be stored and referred to reduce temporal redundancy. Recently, reference frames are recompressed for memory efficiency and bandwidth reduction between a main processor and external memory. However, these algorithms could hurt coding efficiency. Several algorithms have been proposed to reduce the amount of reference memory with minimum quality degradation. They still suffer from quality degradation with fixed-bit allocation. In this paper, we propose an adaptive block-based min-max quantization that considers local characteristics of image. In the proposed algorithm, basic process unit is $8{\times}8$ for memory alignment and apply an adaptive quantization to each $4{\times}4$ block for minimizing quality degradation. We found that the proposed algorithm can obtain around 1.7% BD-bitrate gain and 0.03dB BD-PSNR gain, compared with the conventional fixed-bit min-max algorithm with 37.5% memory saving.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.24 no.1
• /
• pp.31-36
• /
• 2024

Recently, mobile apps that utilize AI technologies are increasing. In the personal mobile environment, performance degradation may occur during the training phase of large AI workload due to limitations in memory capacity. In this paper, we extract memory reference traces of AI workloads and analyze their characteristics. From this analysis, we observe that AI workloads can cause frequent storage access due to weak temporal locality and irregular popularity bias during memory write operations, which can degrade the performance of mobile devices. Based on this observation, we discuss ways to efficiently manage memory write operations of AI workloads using persistent memory-based swap devices. Through simulation experiments, we show that the system architecture proposed in this paper can improve the I/O time of mobile systems by more than 80%.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.2
• /
• pp.445-452
• /
• 2010

In this paper, an attempt has been made to design the controller applicable for H.264 level3 encoder of baseline profile on full hardware basis. The designed controller module first stores the images supplied from CMOS Image Sensor(CIS) at main memory, and then reads or stores the image data in macroblock unit according to encoder operation. The timing cycle of the DMA controller required to process a macroblock is 478 cycles. In order to verify the our design, reference-C encoder, which is compatible to JM 9.4, is developed and the designed controller is verified by using the test vector generated from the reference C code. The number of cycle in the designed DMA controller is reduced by 40% compared with the cycle of using Xilinx MIG.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.5
• /
• pp.19-32
• /
• 1997

So far, the multiple path MINs to provide redundant paths in the traditional UPP MINs have been realized by adding additional hardware such as extra stages, duplicated data links, or multiple copies of sthe MIN. And the traditional MINs do not exploit locality: communication with all processor-memory paris takes the same amount of time. Also so far there has been little progress for exploiting locality of reference in MINs. In this paper, we present a new topology MIN, hybrid MIN that is constructed with 2N-3 SEs which is far fewer SEs than that of traditional MINs. Although the hybrid MIN is constructed with 2N-3 SEs, the hybrid MIN satisfies full access capability (FAC) and has redundant paths(but providing single path for 2 memory modules of each processor). Moreover the has redundant paths (but providing single path for 2 memory modules of each processor). Moreover the Hybrid MIN provides shortcut path between pairs which have frequent dat acommunication (locality of reference). Its performance under varing degrees of localized communication is analyzed.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.23 no.1
• /
• pp.71-76
• /
• 2023

Recently, a memory management strategy that utilizes read and write references separately is attracting attention. This is due to the emergence of new storage media with asymmetric read/write latencies and different read/write access characteristics of software. Existing research assumes that operating systems can differentiate between read/write references that occur on each memory page, but most memory architectures do not support a way to distinguish them. Unlike previous studies, this paper proposes a software method that reflects the read/write characteristics of page references by utilizing the reference and modified bits of each page. Simulations show that the proposed policy has almost similar effects to existing studies with hardware support.

• Journal of Korea Multimedia Society
• /
• v.7 no.8
• /
• pp.1086-1096
• /
• 2004

In case of a multimedia application which deals with streaming data, in terms of cache management, cache loses its efficiency due to weak temporal locality of the data. This means that when data have been brought into cache, much of the data are supposed to be replaced without being accessed again during its service. However, there is a good chance that such multimedia data has a commanding locality in it. In this paper, to take advantage of the memory reference regularity which typically innates even in the multimedia data showing up its weak temporal locality, a method is suggested. The suggested method with the feature of dynamic regular-stride reference prefetching can identify for 2-dimensional array format(block pattern). The suggested method is named as block-reference-prediction-technique (BRPT) since it identifies a block pattern and place an address to be prefetched by the regulation of the block format. BRPT proved to be reassuring to reduce memory reference time significantly for applications having abundant block patterns although new rule has complicated the prefetching system even further.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.4
• /
• pp.878-884
• /
• 2013

Recent C ++ developers take advantage of the many advantages in memory management in the development of reference counting smart pointer. However, these have a problem more than the normal pointer. In this paper, we not only complement these by reference counting smart pointer which pointing a large dynamic object to perform a delete operation to improve performance by creating a thread for the delete operation but also Generalize all data types, we propose a convenient way to operate.

• Korean Journal of Cognitive Science
• /
• v.14 no.2
• /
• pp.27-35
• /
• 2003

The present study, focusing on the stress-shift constructions, examines the tendency of young children to give wrong wide scope interpretation in language acquisition and questions the validity of the guess pattern hypothesis argued by Grodzinsky & Reinhart (1993). According to the hypothesis, children know that they have to construct a reference-set, keep two representations in working memory, and check whether the interpretation needed in the given context justifies selection of competing reference sets, but their working memory is not big enough to hold the materials needed to complete the execution of this task. Hence they give up and resort to a guess. 1 carried out an experiment of 16 Korean children aged 3;9 to 6;2 to find out whether children have more difficulty in the interpretation of stress-shift constructions than of constructions with a nuclear stress, and therefore perform the interpretation of the former by guessing. Assuming that the tendency is caused by a deficiency in contextual computation rather than reference set computation, I try to explain it in terms of pragmatic considerations.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.825-828
• /
• 2005

In this paper, we propose a new nonvolatile unit memory cell and proposal peripheral circuit using the polymer material. Memory that relies on bistable behavior- having tow states associated with different resistances at the same applied voltage - has attracted much interest because of its nonvolatile properties. Such memory may also have other merits, including simplicity of structure and manufacturing, and the small size of memory cells. We have plotted the load line graphs for the use of a polymer memory character, hence we have designed in the band-gap reference shape of a write/erase drive, and then designed in the 2-stage differential amplifier shape of a sense amplifier in the consideration of a low current characteristic of a polymer memory cell. The simulation result shows that is has high gain about 80dB by sensing the very small current.