• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.963-971
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• 1990

This paper proposes a memory intensive VLSI architecture for the realization of real-time 3x3 neighborhood processor based on the distributed arithmetic. The proposed architecture is characterized by a bit serial and multi-kernel parallel processing which exploits the pixel kernel parallelism and concurrency. The chip implements 8 neighborhood processing elements in parallel with efficirnt input and output modules which operate concurrently. Besides the a4chitectural design of a neighborhood processor, the design methodology using module generator concept has been considered and MOGOT(MOdule Generator Oriented VLSI design Tool) has been constructed based on the workstation. Based on these design environments MOGOT, it has been shown that the main part of the suggested architecture can be designed efficiently using 2\ulcorner double metal CMOS technology. It includes design of input delay and data conversion module, look-up table for inner product operation, carry save accumulator, output data converter and delay module, and control module.

• Smart Structures and Systems
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• v.18 no.4
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• pp.663-682
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• 2016

Continuum manipulators as a kind of mechanical arms are useful tools in special robotic applications. In medical applications, like colonoscopy, a maneuverable thin and flexible manipulator is required. This research is focused on developing a basic module for such an application using shape memory alloys (SMA). In the structure of the module three wires of SMA are uniformly distributed and attached to the circumference of a flexible tube. By activating wires, individually or together, different rotation regimes are provided. SMA model is used based on Brinson work. The SMA model is combined to model of flexible tube to provide a composite model of the module. Simulating the model in Matlab provided a platform to be used to develop controller. Complex and nonlinear behavior of SMA make the control problem hard especially when a few SMA actuators are active simultaneously. In this paper, position control of the two degree of freedom module is under focus. An experimental control strategy is developed to regulate a desired position in the module. The simulation results present a reasonable performance of the controller. Moreover, the results are verified through experiments and show that the continuum module of this paper would be used in real modular manipulators.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.112-117
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• 2020

NAND flash memory is a non-volatile memory that retains stored data even without power supply. Internal memory used as a data storage device and solid-state drive (SSD) is used in portable devices such as smartphones and digital cameras. However, NAND flash memory carries the risk of electric shock, which can cause errors during read/write operations, so use error correction codes to ensure reliability. It efficiently recovers bad block information, which is a defect in NAND flash memory. BBT (Bad Block Table) is configured to manage data to increase stability, and as a result of experimenting with the error correction code algorithm, the bit error rate per page unit of 4Mbytes memory was on average 0ppm, and 100ppm without error correction code. Through the error correction code algorithm, data stability and reliability can be improved.

• Journal of the Semiconductor & Display Technology
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• v.21 no.1
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• pp.85-90
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• 2022

In this paper, an asynchronous nonvolatile memory module using a self-diagnosis function was designed. For the system to work, a lot of data must be input/output, and memory that can be stored is required. The volatile memory is fast, but data is erased without power, and the nonvolatile memory is slow, but data can be stored semi-permanently without power. The non-volatile static random-access memory is designed to solve these memory problems. However, the non-volatile static random-access memory is weak external noise or electrical shock, data can be some error. To solve these data errors, self-diagnosis algorithms were applied to non-volatile static random-access memory using error correction code, cyclic redundancy check 32 and data check sum to increase the reliability and accuracy of data retention. In addition, the possibility of application to an asynchronous non-volatile storage system requiring reliability was suggested.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.5
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• pp.737-748
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• 1995

In this paper, we studyed the variables in the design of multichip memory modules with 4M$\times$1bit DRAM chips to construct high capacity and high speed memory modules. The configuration of the module was 8 bit, 16 bit, and 32 bit DRAM modules with employing 0.6 W, 70 nsec 4M$\times$1 bit DRAM chips. We optimized routing area and wiring density by performing the routing experiment with the variables of the chip allocation, module I/O terminal, the number of wiring, and the number of mounting side of the chips. The multichip module was designed to be able to accept MCM-L techiques and low cost PCB materials. The module routing experiment showed that it was an efficient way to align chip I/O terminals and module I/O terminals in parallel when mounting bare chips, and in perpendicular when mounting packaged chips, to set module I/O terminals in two sides, to use double sided substrates, and to allocate chips in a row. The efficient number of wiring layer was 4 layers when designing single sided bare chip mounting modules and 6 layers when constructing double sided bare chip mounting modules whereas the number of wiring layer was 3 layers when using single sided packaged chip mounting substrates and 5 layers when constructing double sided packaged chip mounting substrates. The most efficient configuration was to mount bare chips on doubled substrates and also to increase the number of mounting chips. The fabrication of memory multichip module showed that the modules with bare chips can be reduced to a half in volume and one third in weight comparing to the module with packaged chips. The signal propagation delay time on module substrate was reduced to 0.5-1 nsec.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.507-511
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• 2010

Digital Radio Frequency Memory (below, DRFM) performs RF signal data store, delay and re-transmission. DRFM is wildly used as core module of Jammer, EW simulator, Target Echo Generator etc. This paper suggests a hardware design of DRFM which is composed RF section(RF Input/Output Module, Local Oscillator Module) and Digital section(ADC module, memory, DAC module), and confirm the validity of the propose by the test result.

• The Journal of the Korea Contents Association
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• v.10 no.6
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• pp.80-90
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• 2010

In this paper, we introduce some issues to implement an agent system to support service mobility in home network environment, and describe detailed design method in terminal as well as server agent. Specifically, we describe user recognition module, signaling message receiving/parsing module of terminal agent and signaling message receiving/parsing module, multimedia switching module, memory management module of server agent. We define several parameters managed in IP sharing device and design binding table structure to support mobility. And we utilize M/M/1/K queueing theory to obtain relations between memory size, blocking probability and memory utilization. From the obtained results, we show that memory size can be predicted in server agent mounted on IP sharing device.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2010.05a
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• pp.572-573
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• 2010

Vibration analysis of Fine-pitch Ball Grid Array (FBGA) packages mounted on a Printed Circuit Board (PCB) subjected to harmonic excitation is performed by using finite element method (FEM). A finite element model of a memory module is composed of three main parts, packages, simplified solder balls and bare PCB. At first, natural frequencies and mode shapes of the developed model were confirmed experimentally. Secondly, the harmonic excitation experiment for the module was carried out at the first natural frequency of the memory module, and it was verified with the simulation by using mode superposition method at a constant acceleration.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.429-432
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• 2000

The new MPEG-4 video coding standard enables content-based functionalities. In order to support the philosophy of the MPEG-4 visual standard, each frame of video sequences should be represented in terms of video object planes (VOP’s). In other words, video objects to be encoded in still pictures or video sequences should be prepared before the encoding process starts. Therefore, it requires a prior decomposition of sequences into VOP’s so that each VOP represents a moving object. A parallel processing system is required an automatic segmentation to be processed in real-time, because an automatic segmentation is time consuming. This paper addresses the parallel processing: system for an automatic segmentation for separating moving object from the background in image sequences. The proposed parallel processing system comprises of processing elements (PE’s) and a multi-access memory system (MAMS). Multi-access memory system is a memory controller to perform parallel memory access with the variety of types: horizontal, vertical, and block access way. In order to realize these ways, a multi-access memory system consists of a memory module selection module, data routing modules, and an address calculation and routing module. The proposed system is simulated and evaluated by the CADENCE Verilog-XL hardware simulation package.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.6
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• pp.231-237
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• 2004

Current paper introduces the multimedia functional module and related interface development for digital TV. The module is developed for displaying the image captured by digital still camera, camcorder, or PC in the digital TV. For these purposes, the module has the interface circuit for accessing five media type of memory cards. It decodes JPEG, BMP, or TIFF image date saved in the memory card and converts the image data to analog RGB signal. It also supports three types of output image size from HD(High Definition) to WXGA(Wide Extended Graphics Array) resolution. So the introduced module could be adopted in all kinds of digital TV set.