• Journal of Information Processing Systems
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• 제4권4호
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• pp.133-144
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• 2008

Clusters have become a popular alternative for building high-performance parallel computing systems. Today's high-performance system area network (SAN) protocols such as VIA and IBA significantly reduce user-to-user communication latency by implementing protocol stacks outside of operating system kernel. However, emerging parallel applications require a significant improvement in communication latency. Since the time required for transferring data between host memory and network interface (NI) make up a large portion of overall communication latency, the reduction of data transfer time is crucial for achieving low-latency communication. In this paper, Eager Data Transfer (EDT) mechanism is proposed to reduce the time for data transfers between the host and network interface. The EDT employs cache coherence interface hardware to directly transfer data between the host and NI. An EDT-based network interface was modeled and simulated on the Linux-based, complete system simulation environment, Linux/SimOS. Our simulation results show that the EDT approach significantly reduces the data transfer time compared to DMA-based approaches. The EDTbased NI attains 17% to 38% reduction in user-to-user message time compared to the cache-coherent DMA-based NIs for a range of message sizes (64 bytes${\sim}$4 Kbytes) in a SAN environment.

• 전자공학회논문지A
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• 제33A권7호
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• pp.261-268
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• 1996

Hardware-software codesign becomes improtant to effectively sagisfy perfomrance goals, because designers can trade-off in the way hardware and software components work teogether to exhibit a specified behavior. In this paper, a hardware-software pratitioning algorithm is presetned, in which the system behavioral description containing a mixture of hardware and software components is partitioned into hardware part and software part. The partitioning algorithm tries to minimize the given cost function under constraints on hardware resources or latency. Recursive moving of operations between the hardware and software parts is used to find a near optimum partition and the list scheduling approach is used to estimate the hardware area and latency. Since memory may take substantial protion of the hardware part, memory cost is included in sthe hardware cost. Experimental resutls show that our algorithm is effective.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권1호
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• pp.80-90
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• 2016

Thanks to superior leakage energy efficiency compared to SRAM cells, STTRAM cells are considered as a promising alternative for a memory element in on-chip caches. However, the main disadvantage of STTRAM cells is high write energy and latency. In this paper, we propose a low-cost write filter (WF) cache which resides between the load/store queue and STTRAM-based L1 data cache. To maximize efficiency of the WF cache, the line allocation and access policies are optimized for reducing energy consumption of STTRAM-based L1 data cache. By efficiently filtering the write operations in the STTRAM-based L1 data cache, our proposed WF cache reduces energy consumption of the STTRAM-based L1 data cache by up to 43.0% compared to the case without the WF cache. In addition, thanks to the fast hit latency of the WF cache, it slightly improves performance by 0.2%.

• Journal of Computing Science and Engineering
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• 제3권3호
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• pp.181-194
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• 2009

Flash memory is increasingly being used in a wide range of storage applications because of its low power consumption, low access latency, small form factor, and high shock resistance. However, the current platforms for flash memory software development do not meet the ever-increasing requirements of flash memory applications. This paper presents three different hardware platforms for flash memory/NVRAM (non-volatile RAM) software development that overcome the limitations of the current platforms. The three platforms target different types of host system and provide various features that facilitate the development and verification of flash memory/NVRAM software. In this paper, we also demonstrate the usefulness of the three platforms by implementing three different types of storage system (one for each platform) based on them.

• 대한임베디드공학회논문지
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• 제15권6호
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• pp.299-305
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• 2020

We have developed a scheduler that additionally consider network performance by extending the Kubernetes developed to manage lots of containers in cloud computing nodes. The network delay adapt characteristics of the compute nodes were learned during server operation and the learned results were utilized to develop placement algorithm by considering the existing measurement units, CPU, memory, and volume together, and it was confirmed that the low delay network service was provided through placement algorithm.

• 대한전자공학회논문지SD
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• 제46권8호
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• pp.41-52
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• 2009

Motion JPEG2000과 같은 동영상 압축 시스템에서는 데이터 메모리에 대한 빈번한 접근이 전체 시스템에 큰 병목 현상이 된다. 이처럼 시스템에서 요구하는 메모리의 대역폭을 감소시키기 위해서, 본 논문은 약간의 화질 손실이 있는 새로운 embedded compression(EC) 알고리즘과 구조를 고안하였다. 또한, 메모리 내의 압축된 데이터에 임의 접근성(Random Accessibility)과 짧은 지연 시간(Latency)을 보장하기 위해서 매우 단순하면서도 효율적인 entropy 부호화 방법을 제안하였다. 본 논문에서는 JPEG2000 표준안 알고리즘에는 어떠한 변경도 하지 않으면서, 제안한 multi-mode 알고리즘을 통해 JPEG2000 시스템에서 요구하는 메모리의 대역폭의 감소(약 52${\sim}$81%) 와 코드블록 메모리의 크기를 약 2 배 이상 감소시킬 수 있었다.

• 생명과학회지
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• 제19권3호
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• pp.403-410
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• 2009

본 연구는 청소년기 흰쥐를 대상으로 4주간의 저강도 트레드밀 운동이 기억력과 해마 신경세포생성, BDNF, Trkb, 중격 콜린세포에 미치는 효과를 조사하기 위하여 수행되었다. 먼저 운동이 기억력에 미치는 효과를 step-through avoidance에서 검사한 결과 운동을 실시했던 흰쥐의 retention latency가 대조군에 비해 유의하게 증가되어 기억력 향상을 나타내었다. 이후 기억력 향상기전으로 해마에서 신경세포증식과 BDNF 및 TrkB 단백질 발현을 정량화 한 결과에서도 운동군의 신경세포 생성율과 BDNF와 TrkB 단백질 발현 모두 대조군에 비해 유의하게 증가된 것으로 나타났다. 게다가 운동을 통한 전뇌 콜린세포 수의 증가가 해마 신경세포생성과 BDNF 발현 증가에 기여하는 것으로 나타났다. 이러한 결과는 청소년기 운동이 기억력 향상에 도움이 될 수 있음을 보여주는 것이다.

• Toxicological Research
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• 제24권3호
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• pp.183-188
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• 2008

The behavioral phenotypes of out-bred ICR mice were compared with those of in-bred C57BL/6 and BALB/c mice. In particular, this study examined the locomotor activity and two forms of hippocampus-dependent learning paradigms, passive avoidance and object recognition memory. The basal open-field activity of the ICR strain was greater than that of the C57BL/6 and BALB/c strains. In the passive avoidance task, all the mice showed a significant increase in the cross-over latency when tested 24 hours after training. The strength of memory retention in the ICR mice was relatively weak and measurable, as indicated by the shorter cross-over latency than the C57BL/6 and BALB/c mice. In the object recognition memory test, all strains had a significant preference for the novel object during testing. The index for the preference of a novel object was lower for the ICR and BALB/c mice. Nevertheless, the variance and the standard deviation in these strains were comparable. Overall, these results confirm the strain differences on locomotor activity and hippocampus-dependent learning and memory in mice.

• 약학회지
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• 제51권6호
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• pp.409-414
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• 2007

Acetylcholinesterase (AChE) plays a role in the progression of Alzheimer's disease (AD). In this study, we examined the improving effect of L-theanine, a major amino acid in Japanese green tea (Camellia sinensis) on the scopolamine (1 mg/kg/mouse)-induced memory dysfunction in mice. Treatment with L-theanine (2, 4 mg/kg/mouse p.o.) in the drinking water for 7 days reversed the scopolamine-induced latency time and distance in the water maze test, latency time in the passive avoidance test, and inhibited AChE activity. This study suggests that L-theanine may be a useful agent for prevention of progression of AD.

• 대한임베디드공학회논문지
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• 제18권1호
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• pp.31-40
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• 2023

Recent advances in flash technologies, such as 3D processing and multileveling schemes, have successfully increased the flash capacity. Unfortunately, these technology advances significantly degrade flash's reliability due to a smaller cell geometry and a finer-grained cell state control. In this paper, we propose an asymmetric BER-aware reliability optimization technique (aBARO), new flash optimization that improves the flash reliability. To this end, we first reveal that bit errors of 3D NAND flash memory are highly skewed among flash cell states. The proposed aBARO exploits the unique per-state error model in flash cell states by selecting the most error-prone flash states and by forming narrow threshold voltage distributions (for the selected states only). Furthermore, aBARO is applied only when the program time (tPROG) gets shorter when a flash cell becomes aging, thereby keeping the program latency of storage systems unchanged. Our experimental results with real 3D MLC and TLC flash devices show that aBARO can effectively improve flash reliability by mitigating a significant number of bit errors. In addition, aBARO can also reduce the read latency by 40%, on average, by suppressing the read retries.