• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.10 s.113
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• pp.929-934
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• 2006

In the paper, we suggest a simpler synthesis technique for capacitively-coupled match circuit(CCMC) which have a function of DC block and impedance matching simultaneously, and introduce a stability margin analysis technique for designing microwave amplifier under conditionally stable state. Stability margin analysis is used to determine optimum match point that ensure maximum gain under the given stability margin. It can reduce time consuming work for selecting match points in the conditionally stable state. Also, suggested miniaturization scheme of matching network is distinguished from previous work with respect to reducing deterministic parameters for CCMC synthesis. To verify utility of suggested method, 24 GHz gain block is fabricated under conditionally stable state using an internal thin-film fabrication process, Measured results show a stable gain of 10 dB and flatness of 1 dB, which is well coincident with simulated one.

• Journal of the Korean Institute of Navigation
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• v.25 no.1
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• pp.53-60
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• 2001

This paper presents the fabrication of the LNA which is operating at 2.13 ~ 2.16 GHz for IMT-2000 front-end receiver using series feedback and resistive decoupling circuit. Series feedback added to the source lead of a GaAs FET keeps the low noise characteristics and drops the input reflection coefficient of a low noise amplifier simultaneously. Also, it increases the stability of the LNA. Resistive decoupling circuit is suitable for input stage matching because a signal at low frequency is dissipated by a resistor in the matching network. The amplifier consists of GaAs FET ATF-10136 for low noise stage and VNA-25 which is internally matched MMIC for high gain stage. The amplifier is fabricated with both the RF circuits and self bias circuit on the Teflon substrate with 3.5 permittivity. The measured results of the LNA which is fabricated using the above design technique are presented more than 30 dB in gain, PldB 17 dB and less than 0.7 dB in noise figure, 1.5 in inputㆍoutput SWR(Standing Wave Ratio).

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.3
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• pp.489-496
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• 2019

In this paper, we design and fabricate an ultra small dual crossed dipole antenna operating at 2.4 GHz frequency. In order to miniaturize the size of the antenna so that it can be applied to a mobile device, a cross dipole is disposed on the upper two layers and a reflection plane, a horizontal matching circuit and a ground plane are arranged on each layer. The circuit was connected by a vertical through-hole. The size of the fabricated antenna is $21.61mm{\times}16.88mm{\times}1.27mm$, the measured reflection coefficient is -31.5 dB, and the bandwidth below -10 dB is 112 MHz. In addition, since the gain of the antenna is -4 dBi, it has the omnidirectional radiation characteristic, so it can be applied to various fields as an antenna for mobile devices.

• Journal of IKEEE
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• v.26 no.3
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• pp.456-461
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• 2022

In this paper, a two-stage single-ended power amplifier (PA) with broadband gain characteristics was presented by utilizing a radio frequency (RF) transformer (TF), which is essential for a differential amplifier. The bandwidth of a PA can be improved by designing TF to have broadband characteristics and then applying it to the inter-stage matching network (IMN) of a PA. For broadband gain characteristics while maintaining the performance and area of the existing PA, an IMN was implemented on an monolithic microwave integrated circuit (MMIC) and a multi-layer printed circuit board (PCB), and the simulation results were compared. As a result of simulating the PA module designed using InGaP/GaAs HBT model, it has been confirmed that the PA employing the proposed design method has an improved fractional bandwidth of 19.8% at a center frequency of 3.3GHz, while the conventional PA showed that of 11.2%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.8
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• pp.1705-1712
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• 2004

This paper presents a new low-cost RF Built-In Self-Test (BIST) circuit for measuring transducer voltage gain, noise figure and input impedance of 5.25GHz low noise amplifier (LNA). The BIST circuit is designed using 0.18${\mu}{\textrm}{m}$ SiGe technology. The test technique utilizes input impedance matching and output transient voltage measurements. The technique is simple and inexpensive. Total chip size has additional area of about 18% for BIST circuit.

• The Transactions of the Korean Institute of Power Electronics
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• v.3 no.4
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• pp.353-364
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• 1998

This paper presents a systematic approach to the modeling of power electronic circuits with systemlongrightarrowlevel simulation l languages. It is shown that a circuit model reduces to one of four basic types according to input/output conditions. The e elementary models for single series components and shunt components are derived which are integrated to develop a m model of given converter circuit. The constraints imposed on the model development-matching input/output conditions a and avoiding algebraic loop-are discussed in relation to the realization example of a buck converter circuit model. It is s shown that the constraints can always be fullfilled by introducing fictitious interface blocks, which is generalized to the c concept of model transformation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.635-641
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• 2004

This paper presents a new low-cost RF Built-In Self-Test (BIST) circuit for measuring transducer voltage gain, noise figure and input impedance of 5.25GHa low noise amplifier (LNA). The BIST circuit is designed using 0.18${\mu}{\textrm}{m}$ SiGe technology. The test technique utilizes input impedance matching and output transient voltage measurements. The technique is simple and inexpensive. Total chip size has additional area of about 18% for BIST circuit.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.8
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• pp.862-877
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• 2008

In this paper, two types of wideband 3-dB ring hybrids are compared and discussed to show the ring hybrid with a set of coupled-line sections better. However, the better one still has a realization problem that perfect matching can be achieved only with -3 dB coupling power. To solve the problem, a set of coupled-line sections with two shorts is synthesized using one- and two-port equivalent circuits and design equations are derived to have perfect matching, regardless of the coupling power. Based on the design equations, a modified ${\Pi}-type$ of transmission-line equivalent circuit is newly suggested. It consists of coupled-line sections with two shorts and two open stubs and can be used to reduce a transmission-line section, especially when its electrical length is greater than ${\pi}$. Therefore, the $3\;{\lambda}/4$ transmission-line section of a conventional ring hybrid can be reduced to less than ${\pi}/2$. To verify the modified ${\Pi}-type$ of transmission- line equivalent circuit, two kinds of simulations are carried out; one is fixing the electrical length of the coupled-line sections and the other fixing its coupling coefficient. The simulation results show that the bandwidths of resulting small transmission lines are strongly dependent on the coupling power. Using modified and conventional ${\Pi}-types$ of transmission-line equivalent circuits, a small ring hybrid is built and named a compact wideband coupled-line ring hybrid, due to the fact that a set of coupled-line sections is included. One of compact ring hybrids is compared with a conventional ring hybrid and the compared results demonstrate that the bandwidth of a proposed compact ring hybrid is much wider, in spite of being more than three times smaller in size. To test the compact ring hybrids, a microstrip compact ring hybrid, whose total transmission-line length is $220^{\circ}$, is fabricated and measured. The measured power divisions($S_{21}$, $S_{41}$, $S_{23}$ and $S_{43}$) are -2.78 dB, -3.34 dB, -2.8 dB and -3.2 dB, respectively at a design center frequency of 2 GHz, matching and isolation less than -20 dB in more than 20 % fractional bandwidth.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.186-192
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• 2012

Half-rail stacked drivers are used to reduce power consumption of the drivers for synchronous buck converters. In this paper, the stacked driver is optimized by matching the average charging and discharging currents used by high-side and low-side drivers. By matching the two currents, the average intermediate bias voltage can remain constant without the aid of the voltage regulator as long as the voltage ripple stays within the window defined by the hysteresis of the regulator. Thus the optimized driver in this paper can minimize the power consumption in the regulator. The current matching requirement yields the value for the intermediate bias voltage, which deviates from the half-rail voltage. Furthermore the required capacitance is also reduced in this design due to decreased charging current, which results in significantly reduced die area. The detailed analysis and design of the stacked driver is verified through simulations done using 5V MOSFET parameters of a typical 0.35-${\mu}m$ CMOS process. The difference in power loss between the conventional half-rail driver and the proposed driver is less than 1%. But the conventional half-rail driver has excess charge stored in the capacitor, which will be dissipated in the regulator unless reused by an external circuit. Due to the reduction in the required capacitance, the estimated saving in chip area is approximately 18.5% compared to the half-rail driver.

• Journal of Electrical Engineering and Technology
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• v.11 no.6
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• pp.1656-1663
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• 2016

A capacitive wireless power transfer (C-WPT) system uses an electric field to transmit power through a physical isolation barrier which forms a pair of ac link capacitors between the metal plates. However, the physical dimension and low dielectric constant of the interface medium severely limit the effective link capacitance to a level comparable to the main switch output capacitance of the transmitting circuit, which thus narrows the soft-switching range in the light load condition. Moreover, by fundamental limit analysis, it can be proved that such a low link capacitance increases operating frequency and capacitor voltage stress in the full load condition. In order to handle these problems, this paper investigates optimal design of double matching transformer networks for C-WPT. Using mathematical analysis with fundamental harmonic approximation, a design guideline is presented to avoid unnecessarily high frequency operation, to suppress the voltage stress on the link capacitors, and to achieve wide ZVS range even with low link capacitance. Simulation and hardware implementation are performed on a 5-W prototype system equipped with a 256-pF link capacitance and a 200-pF switch output capacitance. Results show that the proposed scheme ensures zero-voltage-switching from full load to 10% load, and the switching frequency and the link capacitor voltage stress are kept below 250 kHz and 452 V, respectively, in the full load condition.