• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.1
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• pp.51-56
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• 1981

A new I2L process for a high performance I2L structure is proposed. The modifiedstructure consists of a heavily doped extrinsic base and lowly doped intrinsic base where the collector regions are self-alignment with the intrinsic base regions. The proposed process untilizes spin-on sources as the diffusion sources and the self-alignment of collectors is achieved by using the hardened spin-on source as a diffusion mask. Test devices including a 13-stage ring oscillator have been fabricated by the proposed process on n/n+ silicon wafers with 6.5$\mu$m epitaxial layer. The maximum upward current gain of npn transistors is 8 for a three collector I2L cell. The speed-power product and minimum propagation delay for a one collector structure are 3.5 pJ and 50 ns, respectively.

• Journal of the Korean Solar Energy Society
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• v.32 no.5
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• pp.102-107
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• 2012

Halogen lamp was applied to fabricate the selective emitter crystalline silicon solar cell. In selective emitter structure, the recombination of minority carriers is reduced with heavily doped emitter under metal grid, consequently improving the conversion efficiency. Laser selective emitter process which is recently used the most generally induces the damage on the silicon surface. However the lamp has enough heat to form heavily doped emitter layer by diffusing phosphorus from PSG without surface damage. In this work, we have studied to find the design and the suitable condition for halogen lamp such as power, time, temperature and figured out the possibility to fabricate the selective emitter silicon solar cell by lamp heating. The sheet resistance with $100{\Omega}/{\Box}$ was lower to $50{\Omega}/{\Box}$ after halogen lamp treatment. Heat transfer to lightly doped emitter region was blocked by using the shadow mask.

• Journal of the Korean Institute of Telematics and Electronics
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• v.13 no.3
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• pp.22-27
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• 1976

For linear IC design, one has to know the epi thickness, resistivity, and structure of buried island inserted between epi and substrate because the mask structure can only be changed for linear IC consisted of various type of transistors to be made for desired specific function. The interrelation of IC operational and saturation voltages with epi resistivity, theckness and divice structure are studied and presented in graphic forms so that IC design engineers can utilize them.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.2
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• pp.47-53
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• 1984

Breakdown characteristics, specifically, soft breakdown phenomena of the PN junction isolation were studied in terms of their dependence on the mask misaliglment and the amount of process-related defects. Varying the distance between the buried layer and the isolation by intentional misalignment of the isolation masts had no effects on the soft breakdown phenomena except for the change of the breakdown voltage. The soft breakdown phenomena, as characterized as a state of excessive reverse current below the breakdown voltage, were found out to result mainly from the oxidation-induced stacking faults (OSF) introduced during the fabrication process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.468-470
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• 1999

One of the most critical problem in etching of platinum was generally known that the etch slope was gradual. therefore, the addition of $N_2$ gas into the Ar/C1$_2$ gas mixture, which has been proposed the optimized etching gas combination for etching of platinum in our previous article, was performed. The selectivity of platinum film to oxide film as an etch mask increased with the addition of N2 gas, and the steeper etch slope over 75 $^{\circ}$ could be obtained. These phenomena were interpreted the results the results of a blocking layer such as Si-N or Si-O-N on the oxide mask. Compostional analysis was carried out by X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectrometry (SIMS). Moreover, it could be obtained the higher etch rate of Pt film and steeper profile without residues such as p.-Cl and Pt-Pt ant the addition N\ulcorner of 20 % gas in Ar(90)/Cl$_2$(10) Plasma. The Plasma characteristic was extracted from optical emissionspectroscopy (OES).

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.673-681
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• 2014

In this paper, a novel low specific on-resistance SOI LDMOS Device with P+P-top layer in the drift region is proposed and investigated using a two dimensional device simulator, MEDICI. The structure is characterized by a heavily-doped $P^+$ region which is connected to the P-top layer in the drift region. The $P^+$ region can modulates the surface electric field profile, increases the drift doping concentration and reduces the sensitivity of the breakdown voltage on the geometry parameters. Compared to the conventional D-RESURF device, a 25.8% decrease in specific on-resistance and a 48.2% increase in figure of merit can be obtained in the novel device. Furthermore, the novel $P^+P$-top device also present cost efficiency due to the fact that the $P^+$ region can be fabricated together with the P-type body contact region without any additional mask.

• 한국초전도학회:학술대회논문집
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• v.10
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• pp.165-168
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• 2000

We fabricated ramp-edge Josephson junctions with barriers formed by interface treatments instead of epitaxially grown barrier layers. A low-dielectric Sr$_2$AlTaO$_6$(SAT) layer was used as an ion-milling mask as well as an insulating layer for the ramp-edge junctions. An ion-milled YBa$_2$Cu$_3$O$_{7-x}$ (YBCO)-edge surface was not exposed to solvent through all fabrication procedures. The barriers were produced by structural modification at the edge of the YBCO base electrode using high energy ion-beam treatment prior to deposition of the YBCO counter electrode. We investigated the effects of high energy ion-beam treatment, annealing, and counter electrode deposition temperature on the characteristics of the interface-controlled Josephson junctions. The junction parameters such as T$_c$, I$_c$c, R$_n$ were measured and discussed in relation to the barrier layer depending on the process parameters.

• Korean Chemical Engineering Research
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• v.44 no.5
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• pp.513-519
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• 2006

We developed two kinds of the microchip for application to electrophoresis based on both glass and quartz employing the MEMS fabrications. The poly-Si layer deposited onto the bonding interface apart from channel regions can play a role as the optical slit cutting off the stray light in order to concentrate the UV ray, from which it is possible to improve the signal-to-noise (S/N) ratio of the detection on a chip. In the glass chip, the deposited poly-Si layer had an important function of the etch mask and provided the bonding surface properly enabling the anodic bonding. The glass wafer including more impurities than quartz one results in the higher surface roughness of the channel wall, which affects subsequently on the microflow behavior of the sample solutions. In order to solve this problem, we prepared here the mixed etchant consisting HF and $NH_4F$ solutions, by which the surface roughness was reduced. Both the shape and the dimension of each channel were observed, and the electroosmotic flow velocities were measured as 0.5 mm/s for quartz and 0.36 mm/s for glass channel by implementing the microchip electrophoresis. Applying the optical slit with poly-Si layer provides that the S/N ratio of the peak is increased as ca. 2 times for quartz chip and ca. 3 times for glass chip. The maximum UV absorbance is also enhanced with ca. 1.6 and 1.7 times, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.3
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• pp.67-71
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• 2014

An attempt to grow high quality GaN on silicon substrate using metal organic chemical vapor deposition (MOCVD), herein GaN epitaxial layers were grown on various Si(111) substrates. Thin Platinum layer was deposited on Si(111) substrate using sputtering, followed by thermal annealing to form Pt nano-clusters which act as masking layer during dry-etched with inductively coupled plasma-reactive ion etching to generate nano-patterned Si(111) substrate. In addition, micro-patterned Si(111) substrate with circle shape was also fabricated by using conventional photo-lithography technique. GaN epitaxial layers were subsequently grown on micro-, nano-patterned and conventional Si (111) substrate under identical growth conditions for comparison. The GaN layer grown on nano-patterned Si (111) substrate shows the lowest crack density with mirror-like surface morphology. The FWHM values of XRD rocking curve measured from symmetry (002) and asymmetry (102) planes are 576 arcsec and 828 arcsec, respectively. To corroborate an enhancement of the growth quality, the FWHM value achieved from the photoluminescence spectra also shows the lowest value (46.5 meV) as compare to other grown samples.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.341-341
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• 2012

Recently, oxide semi-conductor materials have been investigated as promising candidates replacing a-Si:H and poly-Si semiconductor because they have some advantages of a room-temperature process, low-cost, high performance and various applications in flexible and transparent electronics. Particularly, amorphous indium-gallium-zinc-oxide (a-IGZO) is an interesting semiconductor material for use in flexible thin film transistor (TFT) fabrication due to the high carrier mobility and low deposition temperatures. In this work, we demonstrated improvement of flexibility in IGZO TFTs, which were fabricated on polyimide (PI) substrate. At first, a thin poly-4vinyl phenol (PVP) layer was spin coated on PI substrate for making a smooth surface up to 0.3 nm, which was required to form high quality active layer. Then, Ni gate electrode of 100 nm was deposited on the bare PVP layer by e-beam evaporator using a shadow mask. The PVP and $Al_2O_3$ layers with different thicknesses were used for organic/inorganic multi gate dielectric, which were formed by spin coater and atomic layer deposition (ALD), respectively, at $200^{\circ}C$. 70 nm IGZO semiconductor layer and 70 nm Al source/drain electrodes were respectively deposited by RF magnetron sputter and thermal evaporator using shadow masks. Then, IGZO layer was annealed on a hotplate at $200^{\circ}C$ for 1 hour. Standard electrical characteristics of transistors were measured by a semiconductor parameter analyzer at room temperature in the dark and performance of devices then was also evaluated under static and dynamic mechanical deformation. The IGZO TFTs incorporating hybrid gate dielectrics showed a high flexibility compared to the device with single structural gate dielectrics. The effects of mechanical deformation on the TFT characteristics will be discussed in detail.