• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.455-456
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• 2013

• The Journal of the Korea Contents Association
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• v.10 no.8
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• pp.59-65
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• 2010

This paper proposes an implementation of a hardware module for transmitting MPEG-2 TS data over the internet protocol (IP)-based network. This implementation consists of two modules; one is an encapsulation module which bridges between n TS packets, where $1\;{\leq}\;n\;{\leq}\;7$, and an IP packets, the other is a packet conversion module which extracts an DSM-CC PS packet from consecutive TS packets and then reconstructing an IP packet. So, these IP packets are carried over 150 megabits per second. Although overall work flow of the proposed DeMUX is based on the reference design of ALTERA, the DeMUX is enhanced by modifying it and performs more functions by adding a packet conversion module. The DeMUX is described by Verilog-HDL (hardware description language) and shows the faithful functionality and throughput through the simulation.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.11 no.4
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• pp.63-69
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• 2012

This paper describes novel scheme of a gray scale capacitive fingerprint image for high-accuracy capacitive sensor chip. The typical gray scale image scheme used a DAC of big size layout or charge-pump circuit of non-volatile memory with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit of charge sharing scheme is proposed, which uses DLC(down literal circuit) based on a neuron MOS(vMOS) and analog simple multiplexor. The detection circuit is designed and simulated in 3.3V, $0.35{\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, a pixel layout size can be reduced and the image resolution can be improved.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.74-78
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• 2006

This paper presents a high-speed pulse-based flip-flop with pseudo MUX-type scan compatible with the conventional master-slave flip-flop with MUX-type scan. The proposed flip-flop was implemented as the standard cell library using Samsung 130nm HS technology. The data-to-output delay and power-delay-product of the proposed flip-flop are reduced by up to 59% and 49%, respectively. By using this flop-flop, ARM11 softcore has achieved the maximum 1GHz operating speed.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.339-340
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• 2006

In this paper, a low-power deblocking filter structure for H.264 video coding algorithm is proposed. By sharing addition hardware for common filter coefficients, we have designed an efficient deblocking filter structure. Proposed deblocking filter utilizes MUX and DEMUX circuits for input data sharing and shows 44.2% reduction for add operation. In the HDL coding simulation and FPGA implementation, we achieved 19.5% and 19.4% gate count reduction, respectively, comparison with the conventional deblocking filter structure.

• Proceedings of the KIEE Conference
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• 2005.10c
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• pp.162-165
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• 2005

종전의 준 랜덤 주파수 캐리어(PRC) 발생기는 스위칭 주파수의 2배 주파수에서 매우 큰 스펙트럼 클러스터가 존재하는 문제점이 있었다. 본 연구에서는 상호 2배 관계를 갖는 고정 주파수의 삼각파 캐리어와 3단계 MUX를 이용하여 종전의 PRC방법의 파워 스펙트럼 확산 성능을 개선하였다. 제안된 방법을 3상 캐스케이드 멀티레벨 인버터에 적용하였으며, PSIM시뮬레이션에 의하여 종전의 방법과 제안된 방법의 파워 스펙트럼을 비교 검토하였다.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.409-412
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• 2000

In this paper we have implemented CH-MUX system which provides customers with various services, i.e. POTS, ISDN, digital leased line and so on, and supports not only UDLC but IDLC network configuration based on existing optical transmission facilities. Also the RCS equipment has been designed and implemented for remote monitoring and control of CH-MUXs. And then this paper has described IPC procedure and proposed other implemental methods of IPC channel. Service providers will be able to design and construct cost-effective access network with RCS and CH-MUX systems.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.197-200
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• 2002

In this paper, presents a 1.8V 8-bit 300MSPS CMOS Subranging Analog to Digital Converter (ADC) with a novel reference multiplex is described. The proposed hか converter is composed of Sub A/D Converter block, MUX (Multiplexer) block and digital block. In order to obtain a high-speed operation, further, a novel dynamic latch, an encoder of novel algorithm and a MUX block are proposed. As a result, this A/D Converter is operated 100MHz input frequence by 300MHz sampling rate.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.1
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• pp.1-5
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• 2010

Recently emphasizing the importance of security such as national major institutions' facilities or major industrial facilities for the maintenance of security/crime prevention due to specialization of the Green Information Technology(G-IT) and Green Ubiquitous Technology(G-UT) industry fields, The Security System Building linked high technology within the government-related organization, enterprise and army the military is urgently required. This paper is about the green USN intelligent an unmanned guard MUX system that receive the signals, from alarm device within surveillance area, with various ways of communication techniques and then transmit to local control center and remote control server trough TCP/IP network. This study enables the mutual senergy effect by realizing a total solution of an unmanned guard system and also significantly contributes to the global/domestic market expansion. That can be applied to the crime prevention/security fields in the Green Ubiquitous Environment Implemented Business(survalance-Home, Gu-City, Gu-Health, etc.), and will contribute to expand companies with international competitiveness that can provide the Green Ubiquitous Vision(Gu-Vision).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.6
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• pp.51-58
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• 2002

In this paper, a 155/311 Mb/s MUX/DEMUX chip using ECL macrocell away has been developed with a single device. This device for a 2.5 Gb/s SDH based transmission system is to interleave the parallel data of 51 Mb/s into 155 Mb/s(or 311 Mb/s) serial data output, and is to interleave a serial input bit stream of 155 Mb/s(or 311 Mb/s) into the parallel output of 51 Mb/s. The input and output of the device ate TTL compatible at the low-speed end, but 100k ECL compatible at the high-speed end. The device has been fabricated with Motorola ETL3200 macrocell away The fabricated chip shows the typical phase margin of 180 degrees and output data skew less than 220ps at the high-speed end.