JSTS:Journal of Semiconductor Technology and Science

  • 제6권2호
  • /
  • Pages.74-78
  • /
  • 2006
  • /
  • 1598-1657(pISSN)
  • /
  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

High Speed Pulse-based Flip-Flop with Pseudo MUX-type Scan for Standard Cell Library

  • 발행 : 2006.06.30
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

This paper presents a high-speed pulse-based flip-flop with pseudo MUX-type scan compatible with the conventional master-slave flip-flop with MUX-type scan. The proposed flip-flop was implemented as the standard cell library using Samsung 130nm HS technology. The data-to-output delay and power-delay-product of the proposed flip-flop are reduced by up to 59% and 49%, respectively. By using this flop-flop, ARM11 softcore has achieved the maximum 1GHz operating speed.

키워드

참고문헌

  1. V. Zyuban, 'Optimization of scannable latches for low energy,' IEEE Trans. VLSI Systems, vol. 11, no. 5, pp.778-788, Oct. 2003 https://doi.org/10.1109/TVLSI.2003.814322
  2. Franco Ricci, and et. al., 'A 1.5 GHz 90 nm embedded microprocessor core,' International Symposium on VLSI Circuits, pp.l2-l5, 16-18 June 2005 https://doi.org/10.1109/VLSIC.2005.1469322
  3. J.P. Hurst and N. Kanopoulos, 'Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits,' Test Symposium, Proceedings of the Fourth Asian, pp.346-352, 23-24 Nov. 1995 https://doi.org/10.1109/ATS.1995.485359