• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.687-688
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• 2011

This paper presents a design method for combinational digital logic systems using time domain based multiplexing(TDBM) and common multi-terminal extension decision diagrams(CMTEDD). The proposed method can reduce the 1)hardware, 2)logic levels and 3)pins. In the logic system design, we use two types of decision diagrams(DDs), that is the common binary decision diagrams(CBDDs) and CMTEDDs. Also, we propose an algorithms to derive common multiple-terminal binary decision diagrams(CMTBDD) from CBDDs, and CMTEDDs from CMTBDDs. The CMTEDDs over CBDDs is more compactness in terms of number of non-terminal nodes, where the nodes for output selection variables are not included in the non-terminal nodes. In the logic design, each non-terminal nodes of an CBDDs and an CMTEDDs is realized by a multiplexer(MUX). In addition, we compare the proposed TDBM realization with the conventional one.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.8A
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• pp.821-828
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• 2008

In this paper, we present an optimized design of RS(23,17) decoder for UWB, which uses the pipeline structured-modified Euclidean(PS-ME) algorithm. Firstly, the modified processing element(PE) block is presented in order to get rid of degree comparison circuits, registers and MUX at the final PE stage. Also, a degree computationless decoding algorithm is proposed, so that the hardware complexity of the decoder can be reduced and high-speed decoder can be implemented. Additionally, we optimize Chien search algorithm, Forney algorithm, and FIFO size for UWB specification. Using Verilog HDL, the proposed decoder is implemented and synthesized with Samsung 65nm library. From synthesis results, it can operate at clock frequency of 250MHz, and gate count is 17,628.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.5
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• pp.63-74
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• 2001

Modular exponentiation is an essential operation required for implementations of most public key cryptosystems. This paper presents two architectures for modular exponentiation using the Montgomery modular multiplication algorithm combined with two binary exponentiation methods, L-R(Left to Left) algorithms. The proposed architectures make use of MUXes for efficient pre-computation and post-computation in Montgomery\`s algorithm. For an n-bit modulus, if mulitplication with m carry processing clocks can be done (n+m) clocks, the L-R type design requires (1.5n+5)(n+m) clocks on average for an exponentiation. The R-L type design takes (n+4)(n+m) clocks in the worst case.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.4
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• pp.25-31
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• 2017

This paper presents a 270/540/750/1500-Mb/s serial-data transmitter realized in a $0.13-{\mu}m$ CMOS technology for the applications of video data transmission. A low-cost RG-58 copper cable(5C-HFBT-RG6T) is exploited as a transmission medium connected to a single BNC connector, which shows cable loss 45 dB in maximum at 1.5 GHz. RLGC modeling provides an equivalent circuit for SPICE simulations of which characteristics are very similar to the measured cable loss. The loss can be compensated by pre-emphasis at transmitter and equalization at receiver if needed. Measurements of the proposed transmitter chip demonstrate the operations of 270-Mb/s, 540-Mb/s, 750-Mb/s and 1.5-Gb/s, and provide the output voltage levels of $370mV_{pp}$ at 1.5 Gb/s even with the pre-emphasis turned-off. The total power consumption is 104 mW from 1.2/3.3-V supplies and the chip occupies the area of $1.65{\times}0.9mm^2$.

• Proceedings of the Korean Society of Medical Physics Conference
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• 2002.09a
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• pp.468-470
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• 2002

We have designed X-ray detection system and multi-channel data acquisition system for Spiral CT application. X-ray detection system consists of scintillator and photodiode. Scintillator converts X-ray into visible light. Photodiode converts visible light into electrical signal. The multi-channel data acquisition system consists of analog, digital, master and backplane board. Analog board detects electrical signal and amplifies signal by 140dB. Digital board consists of MUX(Multiplex) which routes multi-channel analog signal to preamplifier, and ADC(Analog to Digital Converter) which converts analog signal into digital signal. Master board supplies the synchronized clock and transmits the digital data to image reconstructor. Backplane provides electrical power, analog output and clock signal. The system converts the projected X-ray signal over the detector array with large gain, samples the data in each channel sequentially, and the sampled data are transmitted to host computer in a given time frame. To meet the timing limitation, this system is very flexible since it is implemented by FPGA(Field Programmable Gate Array). This system must have a high-speed operation with low noise and high SNR(signal to noise ratio), wide dynamic range to get a high resolution image.

• Journal of Sensor Science and Technology
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• v.24 no.4
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• pp.252-257
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• 2015

This paper proposes a single slope A/D converter (SSADC) that is possible to process the signal of the ultraviolet, visible and infrared rays with a single chip. And the proposed SSADC is a type of single channel ADC. In the conventional SSADC, it is possible to process the only one signal with a kind of the sensor because the speed of the operating frequency and the slope of ramp signal generated by the ramp generator are fixed. In order to improve the disadvantages, a ramp generator which has variable slope in ramp function is designed and $3{\times}1$ MUX(multiplexer) is adopted so that we can change the speed of the operating frequency and the slope of ramp signal. Therefore, the multiple signal processing of the wanted sensors can be possible. The designed circuit is layout by the $0.35-{\mu}m$ CMOS 2-poly 4-metal technology process and is checked through DRC and LVS tools.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2367-2372
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• 2015

One of various low-density parity-check(LDPC) codes that has been adopted in many communication standards due to its error correction ability is a quasi-cyclic LDPC(QC-LDPC) code, which leads to comparable decoder complexity. One of the main blocks in the QC-LCDC code decoder is a multi-size circular shifter(MSCS) that can perform various size rotation. The MSCS can be implemented with many structures, one of which is based on Banes network. The Benes network structure can perform the normal MSCS operation efficiently, but it cannot use the properties coming from specifications like rotation sizes. This paper proposesd a scheme where the Benes network structure can use the rotation size property with the modification of the control signal generation. The proposed scheme is applied to the MSCS of IEEE 802.16e WiMAX QC-LDPC decoder to reduce the number of MUXes and the critical path delay.

• Journal of Broadcast Engineering
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• v.2 no.1
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• pp.24-35
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• 1997

Basic and transmission video quality testing was performed in real-time mode using hardware video codec based on MPEG-2 MP@ML standard including subsequent transmitting and receiving satellite simulator unit. The double-stimulus Impairment scale method and the double-stimulus continous quality scale method based on CCIR 500-5 were used as an evaluation method. The whole digital broadcasting satellite system consisting of MPEG-2 codec, system mux/demux, channel codec, channel, modem, antenna, etc. was put into the overall video quality testbed and the basic and transmission error quality assessment was performed at various bitrates and BER for an integrated system performance evaluation. In transmission error video quality testing, transmission error video quality maintained on average above 3.9 point on the 5-point scale. The low-bit rate quality such as film mode(@2Mbps) highly depended on the statitical characteristics of video source and maintained on average around 2.7 point.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.12B
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• pp.1728-1735
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• 2011

In this paper, satellite data link waveform is proposed which is based on the waveform of Link-16 but LDPC code is studied instead of CCSK code in order to be optimized to satellite nonlinear channel environment and transmission characteristics. And the DSM (Demux, Selective CH switch, and Mux) transponder structure is suggested which can remove all of the jamming signal out of the transmission signal band and convert uplink hopping frequency to desired ones of downlink. The results of BER and anti-jamming performance analysis shows that the required Eb/No and processing gain in the worst case partial band jammer of the proposed waveform are 2.5dB and 52dB respectively and the anti-jamming capacity improvement of DSM transponder is maximum 2dB.

• Journal of the Semiconductor & Display Technology
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• v.10 no.4
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• pp.7-13
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• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.