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http://dx.doi.org/10.6109/jkiice.2015.19.10.2367

Low-Complexity and High-Speed Multi-Size Circular Shifter With Benes Network Control Signal Optimization for WiMAX QC-LDPC Decoder  

Kang, Hyeong-Ju (School of Computer Science and Engineering, Korea Univ. of Tech. and Edu.)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.19, no.10, 2015 , pp. 2367-2372 More about this Journal
Abstract
One of various low-density parity-check(LDPC) codes that has been adopted in many communication standards due to its error correction ability is a quasi-cyclic LDPC(QC-LDPC) code, which leads to comparable decoder complexity. One of the main blocks in the QC-LCDC code decoder is a multi-size circular shifter(MSCS) that can perform various size rotation. The MSCS can be implemented with many structures, one of which is based on Banes network. The Benes network structure can perform the normal MSCS operation efficiently, but it cannot use the properties coming from specifications like rotation sizes. This paper proposesd a scheme where the Benes network structure can use the rotation size property with the modification of the control signal generation. The proposed scheme is applied to the MSCS of IEEE 802.16e WiMAX QC-LDPC decoder to reduce the number of MUXes and the critical path delay.
Keywords
LDPC decoder; QC-LDPC decoder; cyclic-shifter; multi-size circular shifter;
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  • Reference
1 R. G. Gallager, Low-Density Parity-Check Codes, Cambridge, MA: M.I.T. Press, 1963.
2 D. Oh and K. K. Parhi, "Area efficient controller design of barrel shifters for reconfigurable LDPC decoders," in Proceedings of IEEE International Symposium on Circuits and Systems, pp. 240-243, 2008.
3 B. Xiang, D. Bao, S. Huang, and X. Zeng, “An 847—955 Mb/s 342—397 mW dual-path fully-overlapped QC-LDPC decoder for WiMAX system in 0.13 μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 46, no. 6, pp. 1416-1432, Jun. 2011.   DOI
4 D. Oh and K. K. Parhi, “Low-complexity switch network for reconfigurable LDPC decoders,” IEEE Transactions on Very Large Scale Integration(VLSI) Systems , vol. 18, no. 1, pp. 85-94, Jan. 2010.   DOI
5 V. E. Benes, “Optimal rearrangeable multistage connecting networks,” Bell System Technical Journal , vol. 43, no. 4, pp. 16410-1656, Jul. 1964.
6 R. M. Tanner, D. Sridhara, A. Sridharan, T. E. Fuja, and D. J. Costello, Jr., “LDPC block and convolutional codes based on circulant matrics,” IEEE Transactions on Information Theory, vol. 50, no. 12, pp. 2966-2984, Dec. 2004.   DOI
7 M. Rovini, G. Gentile, and L. Fanucci, “Multi-size circular shifting networks for decoders of structured LDPC codes,” Electronics Letters, vol. 43, no. 17, pp. 938-940, Aug. 2007.   DOI
8 X. Chen, S. Lin, and V. Akella, “QSN—A simple circularshift network for reconfigurable quasi-cyclic LDPC decoders,” IEEE Transactions on Circuits and Systems—II:Express Briefs, vol. 57, no. 10, pp. 782-786, Oct. 2010.   DOI