• 제목/요약/키워드: MOSFET

검색결과 1,585건 처리시간 0.027초

낮은 온저항과 칩 효율화를 위한 Unified Trench Gate Power MOSFET의 설계에 관한 연구 (Design of Unified Trench Gate Power MOSFET for Low on Resistance and Chip Efficiency)

  • 강이구
    • 한국전기전자재료학회논문지
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    • 제26권10호
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    • pp.713-719
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    • 2013
  • Power MOSFET operate voltage-driven devices, design to control the large power switching device for power supply, converter, motor control, etc. We have optimal designed planar and trench gate power MOSFET for high breakdown voltage and low on resistance. When we have designed $6,580{\mu}m{\times}5,680{\mu}m$ of chip size and 20 A current, on resistance of trench gate power MOSFET was low than planar gate power MOSFET. The on state voltage of trench gate power MOSFET was improved from 4.35 V to 3.7 V. At the same time, we have designed unified field limit ring for trench gate power MOFET. It is Junction Termination Edge type. As a result, we have obtained chip shrink effect and low on resistance because conventional field limit ring was convert to unify.

초고주파용 SiGe pMOSFET에 대한 전기적 특성 분석 (Electrical characteristics analysis of SiGe pMOSFET for High frequency)

  • 정학기;고석웅
    • 한국정보통신학회논문지
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    • 제7권3호
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    • pp.474-477
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    • 2003
  • 본 논문에서는 p형 SiGe pMOSFET를 디자인하고 온도에 따른 전기적 특성들을 분석하였다. 채널길이는 0.9$\mu\textrm{m}$로 하였으며, 온도는 300K와 77K일 때의 특성을 조사하였다. 게이트 전압이 -1.5V로 인가되었을 때, 실온에서는 -0.97V의 문턱전압 값을 얻었으나 77K에서는 -1.15V의 문턱전압 값을 얻었다. 이것은 실온에서의 Si pMOSFET가 갖는 문턱전압 값(-1.36V)보다 동작특성이 우수함을 알 수 있었다.

SiC MOSFET의 고온모델 (Silicon Carbide MOSFET Model for High Temperature Applications)

  • 이원선;오충완;최재승;신동현;이형규;박근형;김영석
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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    • pp.5-8
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    • 2001
  • This paper describes the development of SiC MOSFET model for high temperature applications. The temperature dependence of the threshold voltage and mobility of SiC MOSFET is quite different from that of silicon MOSFET. We developed the empirical temperature model of threshold voltage and mobility of SiC MOSFET and implemented into HSPICE. Using this model the MOSFET Id-Vds characteristics as a function of temperature are simillated. Also the SiC CMOS operational amplifieris designed using this model and the temperature dependence of the frequency response, transfer characteristics and slew rate as a function of temperature are analyzed.

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캐리어 전송 모델에 따른 SiGe pMOSFET의 전기적 특성분석 (Analysis of the electrical characteristics for SiGe pMOSFET by the carrier transport models)

  • 김영동;고석웅;정학기;허창우
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2003년도 추계종합학술대회
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    • pp.773-776
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    • 2003
  • 본 논문에서는 p형 SiGe pMOSFET를 디자인하고 온도에 따른 전기적 특성들을 분석하였다. 채널 길이는 0.9$\mu\textrm{m}$로 하였으며, 온도는 300K와 77K일 때의 특성을 조사하였다. 게이트 전압이 -1.5V로 인가되었을 때, 실온에서는 -0.97V의 문턱전압 값을 얻었으나 77K에서는 -1.15V의 문턱전압 값을 얻었다. 이것은 실온에서의 Si pMOSFET가 갖는 문턱전압 값(-1.36V)보다 동작특성이 우수함을 알 수 있었다.

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Grooved Gate MOSFET의 해석적 모델에 관한 연구 (A Study on the Analytical Model for Grooved Gate MOSFET)

  • 김생환;이창진;홍신남
    • 한국통신학회:학술대회논문집
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    • 한국통신학회 1991년도 추계종합학술발표회논문집
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    • pp.205-209
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    • 1991
  • The conventional modeling equations for planar MOSFET can not be directly used for zero or minus junction depth concave MOSFET. In this paper, we suggest a new model which can simulate the electrical characteristics of concave MOSFET. The threshold voltage modeling was achieved using the charge sharing method considering the relative difference of source and drain depletion widths. To analyze the ID-VDS characteristics, the conventional expressions for planar MOSFET were employed with the electrical channel length as an effective channel length and the channel length modulation factor as ${\alpha}$ΔL. By comparing the proposed model with experimental results, we could get reasonably similar curves and we proposed a concave MOSFET conditiion which shows no short channel effect of threshold voltage(V${\gamma}$).

고 집적을 위한 n-channel MOSFET의 소오스/드레인구조의 특성 비교에 관한 연구 (A Study on the Characteristics Comparison of Source/Drain Structure for VLSI in n-channel MOSFET)

  • 류장렬;홍봉식
    • 전자공학회논문지A
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    • 제30A권12호
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    • pp.60-68
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    • 1993
  • Thw VLSI device of submicron level trends to have a low level of reliability because of hot carriers which are caused by short channel effects and which do not appear in a long-channel MOSFET operated in 5V. In order to minimize the generation of hot carrier, much research has been made into various types of drain structures. This study has suggested CG MOSFET (Concaved Gate MOSFET) as new drain structure and compared its electrical characteristics with those of the conventional MOSFET and LDD-structured MOSFET by making use of a simulation method. These three device were assumed to be produced by the LOCOS process and a computer-based analysis(PISCES-2B simulator) was carried out to verify the hot electron-resistant behaviours of the devices. In the present simulation, the channel length of these devises was 1.0$\mu$m and their DC characteristics, such as VS1DT-IS1DT curves, gate and substrate current, potential contours, breakdown voltage and electric field were compared with one another.

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산화막 및 재산화질화산화막의 MOS 캐패시터와 MOSFET의 신뢰성 (Reliability of MOS Capacitors and MOSFET's with Oxide and Reoxidized-Nitrided-Oxide as Gate Insulators)

  • 노태문;이경수;유병곤;남기수
    • 전자공학회논문지A
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    • 제30A권11호
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    • pp.105-112
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    • 1993
  • Oxide and reoxidized-nitrided-oxide were formed by furnace oxidation and rapid thermal processing (RTP). MOS capacitor and n-MOSFET's with those films as gate insulators were fabricated. The electrical characteristics of insulators were evaluated by current-voltage, high-frequency capacitance-voltage (C-V), and time-dependent dielectrical breakdown (TDDB) measurements. The hot carrier effects of MOSFET's were also investigated. Time-dependent dielectrical breakdown (TDDB) characteristics show that the life time of reoxidized-nitrided-oxide films is about 3 times longer than that of oxides. Hot carrier effects reveal that the life time of MOSFET's with reoxidized-nitrided-oxides is about 3 times longer than that of MOSFET's with oxides. Therefore, it is found that the reliability of dielectric films estimated by the hot carrier effects of MOSFET's is consistent with that of dielectric films from TDDB method.

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나노 구조 MOSFET에서의 일반화된 스케일링의 응용 (Application of Generalized Scaling Theory for Nano Structure MOSFET)

  • 김재홍;김근호;정학기;이종인
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2002년도 춘계종합학술대회
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    • pp.275-278
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    • 2002
  • MOSFET의 게이트 길이가 50nm이하로 작아지면 소자를 설계함에 있어 고려해야 하는 많은 문제점들이 존재하게 된다. 본 논문에서는 MOSFET 소자에 대한 문턱 전압 특성을 조사하였다. 소자에 대한 스케일링은 generalized scaling을 사용하였고 게이트 길이 100nm에서 30nm까지 시뮬레이션 하였다. 이때 나노 구조 MOSFET에 대한 스케일링의 한계를 볼 수 있었다. 문턱 전압을 구하는 방법으로는 선형 추출 방법을 사용하였다.

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전기자동차 배터리 충전을 위한 DC - DC컨버터용 Super Junction MOSFET 설계에 관한 연구 (Study on the Design of DC-DC Converter for Super Junction MOSFET Battery Charger of Electric Vehicles)

  • 김범준;홍영성;심관필;강이구
    • 한국전기전자재료학회논문지
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    • 제26권8호
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    • pp.587-590
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    • 2013
  • Release competition and development of eco-friendly vehicles have been conducted violently also automaker, it will be a high growth industry of the charger and battery, which is the driving source of the motor of an electric vehicle. Reduces the on-resistance power elements DC - DC converter for battery charger for electric vehicles, must minimize switching losses. Should have a low on-resistance power than existing products. Compare the Super Junction MOSFET and Planar MOSFET, As a result, super junction MOSFET improve on about 87.4% on-state voltage drop performance than planar MOSFET.

저전력 분야 응용을 위한 32nm 금속 게이트 전극 MOSFET 소자의 게이트 workfunction 의 최적화 (Gate Workfunction Optimization of a 32 nm Metal Gate MOSFET for Low Power Applications)

  • 오용호;김영민
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2005년도 제36회 하계학술대회 논문집 C
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    • pp.1974-1976
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    • 2005
  • The feasibility of a midgap metal gate is investigated for 32nm MOSFET low power applications. The midgap metal gate MOSFET is found to deliver a driving current as high as a bandedge gate one for the low power applications if a proper retrograde channel is used. An adequate design of the retrograde channel is essential to achieve the performance requirement given in ITRS roadmap. In addition, a process simulation is run using halo implants and thermal processes to evaluate the feasibility of the necessary retrograde profile in manufacturing environments. From the thermal budget point of view, the bandedge metal gate MOSFET is more vulnerable to the following thermal process than the midgap metal gate MOSFET since it requires a steeper retrograde doping profile. Based on the results, a guideline for the gate workfunction and the channel profile in the 32 nm MOSFET is proposed.

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