• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.2
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• pp.184-191
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• 1993

Continuous-time integrated filters, implemented in MOS VLSI technology, have been receiving considerable attention. In this paper, a continuous-time fifth order elliptic low-pass MOSFET-C filter has been designed with a cutoff frequency 3,400Hz. First an active RC filter is designed using cascade method which each block can be tunable. And then the resistors of an active RC network are replaced by a linear resistor using NMOS depletion transistors operated in the triode region. This continuous-time MOSFET filter have simpler structure than switched-capacitor filter, so reduce the chip area. The designed MOSFET-C filter characteristics are simulated by PSPICE program.

• ETRI Journal
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• v.46 no.3
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• pp.550-563
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• 2024

A novel inductance simulation circuit employing only two dual-output voltage-differencing buffered amplifiers (DO-VDBAs) and a single capacitance (grounded) is proposed in this paper. The reported configuration is a purely resistor-less realization that provides electronically controllable realized inductance through biasing quantities of DO-VDBAs and does not rely on any constraints related to matched values of parameters. This structure exhibits excellent behavior under the influence of tracking errors in DO-VDBAs and does not exhibit instability at high frequencies. The simple and compact metal-oxide semiconductor (MOS) implementation of the DO-VDBAs (eight MOS per DO-VDBA) and adoption of grounded capacitance make the proposed circuit suitable for on-chip realization from the perspective of chip area consumption. The function of the pure grounded inductance is validated through high pass/bandpass filtering applications. To test the proposed design, simulations were performed in the PSPICE environment. Experimental validation was also conducted using the integrated circuit CA3080 and operational amplifier LF-356.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.2
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• pp.131-139
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• 1996

This paper describes the chaotic neuron model to represent the complicated states of brain and analyzes the dynamical responses of chaotic neuron such as periodic, bifurcation, and chaotic phenomena which are simulated iwth numerical analysis. Next, the chaotic neuron circuit is implemented w ith the analog electronic devices. The transfer function of chaotic neuron is given by summed the linear and nonlinear property. The output function of chaojtic neuron is designed iwth the two cMOS inverters and a feedback resistor. By adjusting the external voltage, the various dynamical properties are demonstrated. In addition, we construt the chaotic neural networks which are composed of the interconnection of chaotic neuroncircuit such as serial, paralle, and layer connection. On the board experiment, we proved the dynamci and chaotic responses which exist in the human brain.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.4 no.1
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• pp.25-31
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• 1979

All the resitors in the active RC filter networks can be relplaced by the switched capacitors. Therefore, An SC filter circuit can be fully integrated using MOS technology. A switched capacitor is much better than a resistor in temperature and linearity characteristics, and the former can be fabricated on the much smaller area then the latter. In this paper, It is given the generalized disign method of the active SC filter from the active RC filter using Bilinear Z-transformation. By SC filtering Techniques using Bilinear Z-transform, It enalbes us to realize the FDNR and Gyrator filters, which could not be realized in the exsisting designs, and it permits the processing of signals at much higher frequenies that many previous designs do. Experiments show that the response of the SC active filter is similiar to that of its prototype active RC filter.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.559-560
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• 2008

In this paper, I proposed 10bits 40MS/s Pipelined A/D converter. The op-amps for SHA and MDAC designed folded-cascode amplifier with gain-booster. And the MOS transistors with a low threshold voltage are employed to low on-resistor and parasitic capacitance. The power dissipation is 119㎽ at 1.2V and 40MS/s

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.1-9
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• 2011

Memristor is a portmanteau of "memory resistor". The resistance of memristor is changed depends on the history of electric charge that passed through the device and it is able to memorize the last resistance after turning off the power supply. This paper presents this device that has a high chance to be the next generation of commercial non-volatile memory and its behavior modeling using SPICE simulation. The memristor MOS content addressable memory (M_CAM) is also designed and simulated using the proposed behavioral model. The proposed M_CAM unit cell area and power consumption show an improvement around 40% and 96%, respectively, compare to the conventional SRAM based CAMs. The M_CAM layout is also implemented using 0.13${\mu}m$ mixed-signal CMOS process under 1.2 V supply voltage.

• Transactions on Electrical and Electronic Materials
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• v.17 no.3
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• pp.172-177
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• 2016

Miller feedback compensation is introduced in a low dropout regulator (LDO) in order to obtain a capacitor-free regulator and improve the fast transient response. The conventional LDO has a limited bandwidth because of the large-size output capacitor and parasitic gate capacitance in the power MOSFET. In order to obtain a stable frequency response without the output capacitor, LDO is designed with resistor-capacitor (R-C) compensation and this is achieved with a connection between the gain-stage and the power MOS. An R-C compensator is suggested to provide a pole and zero to improve the stability. The proposed LDO is designed with the 0.35 μm CMOS process. Simulation testing shows that the phase margin in the Bode plot indicates a stable response, which is over 100^o. In the load regulation, the transient time is within 55 μs when the load current changes from 0.1 to 1 mA.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.6
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• pp.239-245
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• 2016

In this study, a 12 V PWM boost converter was designed with the optimal values of the external components of the power stage was well as the compensation stage for smart electronic applications powered by a battery device. The 12 V boost PWM converter consisted of several passive elements, such as a resistor, inductor and capacitor with a diode, power MOS switch and control IC chip for the control PWM signal. The devices of the power stage and compensation stage were designed to maintain stable operation under a range of load conditions as well as achieving the highest power efficiency. The results of this study were first verified by a simulation in SPICE from calculations of the values of major external elements comprising the converter. The design was also implemented on the prototype PCBboard using commercial IC LM3481 from Texas Instruments, which has a nominal output voltage of 12 V. The output voltage, ripple voltage, and load regulation with the line regulation were measured using a digital oscilloscope, DMM tester, and DC power supply. By configuring the converter under the same conditions as in the circuit simulation, the experimental results matched the simulation results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.68-74
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• 2010

A sub-${\mu}$W CMOS Wien-Bridge oscillator for ultra low power (ULP) radio applications is presented. The Wien-Bridge oscillator is based on an non-inverting opamp amplifier with a closed-loop gain $1+R_2/R_1$ as a means of providing necessary loop gain. An additional RC network provides appropriate phase shift for satisfying the Barkhausen oscillation condition at the given frequency of 1/($2{\pi}RC$). In this design, we propose a novel loop gain control method based on a variable capacitor network instead of a rather conventional variable resistor network. Implemented in $0.18{\mu}m$ CMOS, the oscillator consumes only 560 nA at the oscillation frequency of 22 kHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.72-78
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• 2009

This paper proposes a low phase noise ring voltage controlled oscillator(VCO) with a standard $0.13{\mu}m$ CMOS process for PLL circuit using the VCO-gain-controlled Delay cell. The proposed Delay cell architecture with a active resistor using a MOS transistor. This method can reduced a VCO gain so that improve phase noise. And, Delay cell consist of Wide-Swing Cascode current mirror, Positive Latch and Symmetric load for low phase noise. The measurement results demonstrate that the phase noise is -119dBc/Hz at 1MHz offset from 1.9GHz. The VCO gain and power dissipation are 440MHz/V and 9mW, respectively.