• 한국재료학회:학술대회논문집
• /
• 한국재료학회 2000년도 추계학술발표강연 및 논문개요집
• /
• pp.39-39
• /
• 2000

• 한국세라믹학회지
• /
• 제42권2호
• /
• pp.104-109
• /
• 2005

PbO 완충층의 역할을 확인하기 위해, r.f. magnetron sputtering법을 이용하여 p-type (100) Si 기판 위에 $Pt/Pb_{1.1}Zr_{0.53}Ti_{0.47}O_{3}$와 PbO target으로 Pt/PZT/PbO/Si의 MFIS 구조를 제조하였다. MFIS 구조에 완충층으로 PbO를 삽입함으로써 PZT 박막의 결정성이 크게 향상되었고, 박막의 공정온도도 상당히 낮출 수 있었다. 그리고 XPS depth profile 분석 결과, PbO 증착시 기판온도가 PbO와 Si의 계면에서 Pb의 확산에 미치는 영향을 확인하였다. PbO 완충층을 삽입한 MFIS는 높은 메모리 윈도우와 낮은 누설전류 밀도를 가지는 추수한 전기적 특성을 나타내었다. 특히, 기판온도 $300^{\circ}C$에서 증착된 PbO를 삽입한 Pt/PZT(200nm, $400^{\circ}C)PbO(80nm)/Si$는 9V의 인가전압에서 2.OV의 가장 높은 메모리 윈도우 값을 나타내었다.

• 한국재료학회지
• /
• 제10권4호
• /
• pp.270-275
• /
• 2000

Metal/ferroelectric/insulator/semiconductor(MFIS)-Field Effect Transistor을 위한 Pt/YMnO$_3$/Y$_2$O$_3$/Si 구조를 제조하여 MFIS 구조의 특성에 미치는 $Y_2$O$_3$박막의 영향을 고찰하였다. PLD법을 이용하여 p=type Si(111) 기판 위에 증착시킨 $Y_2$O$_3$박막은 증착온도와 관계없이 (111)방향으로의 우선배향성을 갖고 결정화 되었다. 실리콘 위에 바로 MOCVD법에 의해 강유전체 YMnO$_3$박막을 증착시킨 경우 실리콘과의 계면에서 Mn이 부족한 층이 형성되지만 $Y_2$O$_3$가 실리콘과 YMnO$_3$사이에 삽입된 경우는 $Y_2$O$_3$바로 위에서부터 화학양론비에 일치하는 양질의 YMnO$_3$박막을 얻을 수 있었다. 85$0^{\circ}C$, 100mtorr의 진공분위기에서 열처리한 YMnO$_3$박막은 $Y_2$O$_3$가 삽입된 경우 memory window 값이 $Y_2$O$_3$가 삽입되지 않은 경우보다 더 큰 값을 보였으며 5V에서 1.3V의 값을 보였다.

• 산경연구논집
• /
• 제8권3호
• /
• pp.19-22
• /
• 2017

Purpose - To control exorbitant interest rates, implementation of an interest rate ceiling is a standard practice in microfinance. However, there are pros and cons of such market intervention. Hence, the aim of this short note is to highlight issues and challenges regarding the interest rate cap in microfinance, both from the perspective of clients and institutions. Research design, data, and methodology - While the nature of this short note is explanatory and descriptive, the research methodology used relevant data from the MixMarket and Microcredit Regulatory Authority (MRA) annual reports in Bangladesh. Results - We argue that an interest rate ceiling is detrimental both for the clients and microfinance institutions (MFIs). This market intervention substantially reduces the outreach of MFIs and clients are most likely to pay a higher price in the long-run. Additionally, an interest rate cap also puts severe pressure on new-born and high-cost MFIs to cope with the interest rate ceiling. Conclusions - Although market intervention may be necessary in the short-run, it should not be the ultimate solution to abate high interest in microfinance. Understanding the operational dynamics of MFIs, as well as promoting productivity, efficiency and competition could help to lower the interest rates.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2001년도 하계학술대회 논문집
• /
• pp.58-61
• /
• 2001

Metal-insulator-semiconductor (MIS) C-V properties with high dielectric AIN thin films showed no hysteresis and good interface properties. The dielectric constant of the AIN film calculated from the capacitance at the accumulation region in the capacitance-voltage(C-V) characteristics was about 8. The C-V characteristics of MFIS capacitor showed a hysteresis loop due to the ferroelectric nature of the LiNbO$_3$ thin films. Typical dielectric constant value of LiNbO$_3$ film of MFIS device was about 23. The memory window width was about 1.2V at the gate voltage of $\pm$5 V ranges. Typical gate leakage current density of the MFIS structure was the order of 10$^{-9}$ A/cm$^2$ at the range of within $\pm$500 kV/cm. The ferroelectric capacitors showed no polarization degradation up to about 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulse(peak-to-peak 8V, 50% duty cycle) in the 500kHz.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2003년도 춘계학술대회 논문집 센서 박막재료 반도체 세라믹
• /
• pp.186-189
• /
• 2003

The MFIS capacitors were fabricated using a metalorganic decomposition method. Thin layers of $ZrO_2$ and $CeO_2$ were deposited as a buffer layer on Si substrate and BLT thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated. X -ray diffraction was used to determine the phase of the BLT thin films and the quality of the $ZrO_2$ and $CeO_2$ layer. AES show no interdiffusion and the formation of amorphous $SiO_2$ layer is suppressed by using the $ZrO_2$ and $CeO_2$ film as buffer layer between the BLT film and Si substrate. The width of the memory window in the C-V curves for the $BLT/ZrO_2/Si$ and $BLT/CeO_2/Si$ structure is 2.94 V and 1.3V, respectively. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2004년도 추계학술대회 논문집 전기물성,응용부문
• /
• pp.183-186
• /
• 2004

The metal-ferroelectric-insulator-semiconductor(MFIS) capacitors were fabricated using a metalorganic decomposition (MOD)method. The $CeO_2$ thin films were deposited as a buffer layer on Si substrate and $Bi_{3.25}La_{0.75}Ti_3O_{12}$ (BLT) thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated by varying the $CeO_2$ layer thickness. The width of the memory window in the capacitance-voltage (C-V)curves for the MFIS structure decreased with increasing thickness of the $CeO_2$ layer. Auger electron spectroscopy (AES) and transmission electron microscopy (TEM) show no interdiffusion by using the $CeO_2$ film as buffer layer between the BLT film and Si substrate. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory field-effect-transistors (FETs) with large memory window.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2000년도 하계학술대회 논문집
• /
• pp.743-746
• /
• 2000

Metal-ferroelectric-insulator-semiconductor(MFIS) devices using Pt/$LiNbO_3$/Si structure were successfully fabricated. The dielectric constant of the AIN film calculated from the capacitance in the accumulation region in the capacitance-voltage(C-V) curve was about 8.2. The gate leakage current density of MIS devices using a aluminum electrode showed the least value of 1$\times$$1O^{-8}$A/$cm^2$ order at the electric field of 500kV/cm. The dielectric constant of $LiNbO_3$film on AIN/Si structure was about 23 derived from 1MHz capacitance-voltage (C-V) measurement and the resistivity of the film at the field of 500kV/cm was about 5.6$\times$ $1O^{13}$ $\Omega$.cm.

• Asian Journal of Business Environment
• /
• 제10권3호
• /
• pp.13-22
• /
• 2020

Purpose: Vietnam's financial sector has grown substantially but microfinance institutions (MFIs) still face up many challenges in providing financial services to underserved customer segments, including small businesses, rural populations, and urban migrants. The recent worldwide explosion of fintech, including in Vietnam, promises to fill this gap. The purpose of this paper is to analyze fintech activities in microfinance sector and recommend for fintech adoption of MFIs in Vietnam. Research Design, Data and Methodology: The paper's data is mainly based on international organizations such as Asia Development Bank (ADB), Food and Agriculture Organization of the United Nations (FAO) and Vietnamese organizations such as Vietnam Microfinance Working Group. The authors suggest new directions for microfinance activities in Vietnam. Results: In recent years, the application of fintech in microfinance sector has brought many good results, such as improving the quality of products and services, easy access to many customer groups, and scaling up the operating model. Conclusion: MFIs in Vietnam have developed new products and services by applying fintech. The application of technology and digital solution has supported MFIs in Vietnam to gradually achieve targeted growth through expanding geographical inclusion/scale, enhancing product supply/provision, helping in-depth customer understanding as well as improving operational efficiency.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
• /
• pp.174-174
• /
• 2008

Non-volatile memories using ferroelectric-gate field-effect transistors (Fe-FETs) with a metal/ferroelectric/semiconductor gate stack (MFS-FETs) make non-destructive read operation possible. In addition, they also have features such as high switching speed, non-volatility, radiation tolerance, and high density. However, the interface reaction between ferroelectric materials and Si substrates, i.e. generation of mobile ions and short retention, make it difficult to obtain a good ferroelectric/Si interface in an MFS-FET's gate. To overcome these difficulties, Fe-FETs with a metal/ferroelectric/insulator/semiconductor gate stack (MFIS-FETs) have been proposed, where insulator as a buffer layer is inserted between ferroelectric materials and Si substrates. We prepared $SrBi_2Ta_2O_9$ (SBT) film as a ferroelectric layer and $LaZrO_x$ (LZO) film as a buffer layer on p-type (100) silicon wafer for making the MFIS-FET devices. For definition of source and drain region, phosphosilicate glass (PSG) thin film was used as a doping source of phosphorus (P). Ultimately, the n-channel ferroelectric-gate FET using the SBT/LZO/Si Structure is fabricated. To examine the ferroelectric effect of the fabricated Fe-FETs, drain current ($I_d$) versus gate voltage ($V_g$) characteristics in logarithmic scale was measured. Also, drain current ($I_d$) versus drain voltage ($V_d$) characteristics of the fabricated SBT/LZO/Si MFIS-FETs was measured according to the gate voltage variation.