• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.50-54
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• 2004

A numerical system to extract effective elastic properties of polycrystalline thin-films for MEMS devices is already developed. In this system, the statistical model based on lattice system is used for modeling the microstructure evolution simulation and the key kinetics parameters of given micrograph, grain distributions and deposition process can be extracted by inverse method proposed in the system. In this work, the effects of kinetics parameters on the extraction of effective elastic properties of polycrystalline thin-films are studied by using statistical method. The effects of the fraction of the potential site( $f_{P}$ ) and the nucleation probability( $P_{N}$ ) among the parameters for deposition process of microstructure on the extraction of effective elastic properties of polycrystalline thin-films are studied.d.d.

• Journal of the Korean Society for Precision Engineering
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• v.21 no.6
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• pp.7-14
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• 2004

나노 임프린트 기술은 기존의 광학적 리소그라피 (optical lithography) 기술보다 저렴한 비용으로 나노 구조물을 대량으로 제조할 수 있을 것으로 기대되고 있는 기술이다. 현재까지 반도체 공정기술의 주류를 이루고 있는 광학적인 리소그라피 기술은, 100nm이상의 CD(Critical Dimension)를 가지는 구조물들을 정밀하게 제조하여, 미소전자공학 (microelectronics) 소자, MEMS/MEMS, 광학소자 등의 제품들을 대량으로 생산하는 데에 널리 활용되고 있다. 반도체 소자의 고집적화 경향에 따라 100 nm 이하의 CD를 가지는 나노 구조물들을 제조할 필요성이 높아지고 있지만, 광학적인 방법으로는 광원의 파장보다 작은 구조물들을 제조하기가 어렵다. 보다 짧은 파장을 가지는 광원을 이용하는 리소그라피 장비가 계속적으로 개발되고 있으나, 그에 따른 장비 비용 및 제조 단가가 기하급수적으로 증가하고 있다.(중략)

• Journal of Sensor Science and Technology
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• v.15 no.1
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• pp.53-57
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• 2006

This paper describes a novel processing technique for fabrication of polymer-derived SiCN (silicone carbonitride) microstructures for super-temperature MEMS applications. PDMS (polydimethylsiloxane) mold is fabricated on SU-8 photoresist using standard UV photolithographic process. Liquid precursor is injected into the PDMS mold. Finally, solid polymer structure is cross-linked using HIP (hot isostatic pressure) at $400^{\circ}C$, 205 bar. Optimum pyrolysis and annealing conditions are determined to form a ceramic microstructure capable of withstanding over $1400^{\circ}C$. The fabricated SiCN ceramic microstructure has excellent characteristics, such as shear strength (15.2 N), insulation resistance ($2.163{\times}10^{14}{\Omega}$) and BDV (min. 1.2 kV) under optimum process condition. These fabricated SiCN ceramic microstructures have greater electric and physical characteristics than bulk Si wafer. The fabricated SiCN microstructures would be applied for supertemperature MEMS applications such as heat exchanger and combustion chamber.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.3
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• pp.234-239
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• 2007

This paper describes the TiW ohmic contact characteristics under the surface treatment of the polycrystalline 3C-SiC thin film grown on $SiO_2/Si(100)$ wafers by APCVD. The poly 3C-SiC surface was polished by using CMP(chemical mechanical polishing) process and then oxidized by wet-oxidation process, and finally removed SiC oxide layers. A TiW thin film as a metalization process was deposited on the surface treated poly 3C-SiC layer and was annealed through a RTA(rapid thermal annealing) process. TiW/poly 3C-SiC was investigated to get mechanical, physical, and electrical characteristics using SEM, XRD, XPS, AFM, optical microscope, I-V characteristic, and four-point probe, respectively. Contact resistivity of the surface treated 3C-SiC was measured as the lowest $1.2{\times}10^{-5}{\Omega}cm^2$ at $900^{\circ}C$ for 45 sec. Therefore, the surface treatments of poly 3C-SiC are necessary to get better contact resistance for extreme environment MEMS applications.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2005.05a
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• pp.237-240
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• 2005

The demand of micro electrical mechanical system (MEMS) bio/chemical sensor is rapidly increasing. To prevent the contamination of sensing area, a filtration system is required in on-chip total analyzing MEMS bio/chemical sensor. A nano-filter was mainly applied in some application detecting submicron feature size bio/chemical products such as bacteria, fungi and so on. We suggested a simple nano-filter fabrication process based on replication process. The mother pattern was fabricated by holographic lithography and reactive ion etching process, and the replication process was carried out using polymer mold and UV-imprinting process. Finally the nano-filter is obtained after removing the replicated part of metal deposited replica. In this study, as a practical example of the suggested process, a nano-dot array was replicated to fabricate nano-filter fur bacteria sensor application.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.1-5
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• 2010

We developed a novel micro-electro mechanical systems (MEMS) test socket using silicon on insulator (SOI) substrate with the cantilever array structure. We designed the round shaped cantilevers with the maximum length of $350{\mu}m$, the maximum width of $200{\mu}m$ and the thickness of $10{\mu}m$ for $650{\mu}m$ pitch for 8 mm x 8 mm area and 121 balls square ball grid array (BGA) packages. The MEMS test socket was fabricated by MEMS technology using metal lift off process and deep reactive ion etching (DRIE) silicon etcher and so on. The MEMS test socket has a simple structure, low production cost, fine pitch, high pin count and rapid prototyping. We verified the performances of the MEMS test sockets such as deflection as a function of the applied force, path resistance between the cantilever and the metal pad and the contact resistance. Fabricated cantilever has 1.3 gf (gram force) at $90{\mu}m$ deflection. Total path resistance was less than $17{\Omega}$. The contact resistance was approximately from 0.7 to $0.75{\Omega}$ for all cantilevers. Therefore the test socket is suitable for BGA integrated circuit (IC) packages tests.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.10
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• pp.894-900
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• 2006

This paper reports the fabrication and characterization of $32{\times}32$ thermal cantilever array for nano-scaled memory device applications. The $32{\times}32$ thermal cantilever array with integrated tip heater has been fabricated with micro-electro-mechanical systems(MEMS) technology on silicon on insulator(SOI) wafer using 9 photo masking steps. All of single-level cantilevers(1,024 bits) have a p-n junction diode in order to eliminate any electrical cross-talk between adjacent cantilevers. Nonlinear electrical characteristic of fabricated thermal cantilever shows its own thermal heating mechanism. In addition, n-channel high-voltage MOSFET device is integrated on a wafer for embedding driver circuitry.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.05a
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• pp.497-502
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• 2002

This paper describes a design methodology of a tri-axial silicon-based farce sensor with square membrane by using micromachining technology (MEMS). The sensor has a maximum farce range of 5 N and a minimum force range of 0.1N in the three-axis directions. A simple beam theory was adopted to design the shape of the micro-force sensor. Also the optimal positions of piezoresistors were determined by the strain distribution obtained from the commercial finite element analysis program, ANSYS. The Wheatstone bridge circuits were designed to consider the sensitivity of the force sensor and its temperature compensation. Finally the process for microfabrication was designed using micromachining technology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.874-877
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• 2001

SOI(Silicon-On-Insulator) technology is proposed as an alternative to bulk silicon for MEMS(Micro Electro Mechanical System) manufacturing. In this paper, we fabricated the SOI wafer with uniform active layer thickness by silicon direct bonding and mechanical polishing processes. Specially-designed electrostatic bonding system is introduced which is available for vacuum packaging and silicon-glass wafer bonding for SOG(Silicon On Glass) wafer. We demonstrated thermopile sensor and RF resonator using the SOI wafer, which has the merits of simple process and uniform membrane fabrication.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.379-380
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• 2008

This paper presents a wafer-level package using a Dry Film Resist(DFR) for RF MEMS devices. Vertical interconnection is made through the hole formed on the glass cap. Bonding using the DFR has not only less effects on the surface roughness but also low process temperature. We used DFR as adhesive polymer and made the vertical interconnection through Au electroplating. Therefore, we developed a wafer-level package that is able to be used in RF MEMS devices and vertical interconnection.