• Particle and aerosol research
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• v.5 no.3
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• pp.95-109
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• 2009

A low temperature plasma process has been widely used for semiconductor fabrication and can also be applied for the preparation of solar cell, MEMS or NEMS, but they are notorious in the point of particle contamination. The nano-sized particles can be generated in the low temperature plasma process and they can induce several serious defects on the performance and quality of microelectronic devices and also on the cost of final products. For the preparation of high quality thin films of high efficiency by the low temperature plasma process, it is desirable to increase the deposition rate of thin films with reducing the particle contamination in the plasmas. In this paper, we introduced the studies on the generation and growth of nanoparticles in the low temperature plasmas and tried to introduce the recent interesting studies on nanoparticle generation in the plasma reactors.

• Journal of Sensor Science and Technology
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• v.11 no.1
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• pp.39-47
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• 2002

Optical disk drives read information by replacing a laser beam on the disk track. As information has become larger, the more accurate position control of a laser beam is necessary. In this paper, we report the analysis and fabrication of the micro mirror for optical disk drivers. The mirror was fabricated by using MEMS technology. Especially, the Process using the lapping and polishing step after the bonding of the mirror and electrode plates was employed for the process reliability. The mirror size was $2.5mm{\times}3mm$ and it needed about 35V for displacement of $3.2{\mu}m$.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.5
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• pp.674-680
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• 2017

Touch Screen Panel (TSP) is a widely used personal handheld device and as a large display apparatus. This study examines micro bump fabrication technology for TSP test process. In the testing process, as TSP is changed, should make a new micro bump for probing and modify the testing program. In this paper we use a maskless lithography system to confirm the potential to fabricatemicro bump to reducecost and manufacturing time. The requiredmaskless lithography system does not use a mask so it can reduce the cost of fabrication and it flexible to cope with changes of micro bump probing. We conducted electro field simulation by pitches of micro bump and designed the lithography pattern image for the maskless lithography process. Then we conducted Photo Resist (PR) patterning process and electro-plating process that are involved in MEMS technology to fabricate micro bump.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.107-110
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• 2000

In this experiment, we fabricated pyramid-type silicon tunneling devices in which a tunneling current flow between a micro-tip and Si$_3$N$_4$ thin film membrane. A MEMS process was used for the fabrication of the tunneling devices. The micro-tips were formed on Si wafers by undercutting a differently oriented square of SiO$_2$ with KOH. The stiffness of the Si$_3$N$_4$ films were observed and the model for the stiffness calculation, which is useful in predicting the stiffness even when the stiffness ranges beyond the scope of the normal experimental condition, was suggested.

• Journal of the Korean Society for Precision Engineering
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• v.23 no.3 s.180
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• pp.56-60
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• 2006

A high-resolution shadow mask, or called a nanostencil was fabricated for high resolution lithography. This high-resolution shadowmask was fabricated by a combination or MEMS processes and focused ion beam (FIB) milling. 500 nm thick and $2{\times}2mm$ large membranes wore made on a silicon wafer by micro-fabrication processes of LPCVD, photolithography, ICP etching and bulk silicon etching. A subsequent FIB milling enabled local membrane thinning and aperture making into the thinned silicon nitride membrane. Due to the high resolution of the FIB milling process, nanoscale apertures down to 70 nm could be made into the membrane. By local deposition through the apertures of nanostencil, nanoscale patterns down to 70 nm could be achieved.

• Journal of Fisheries and Marine Sciences Education
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• v.19 no.3
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• pp.366-372
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• 2007

This paper presents the fabrication techniques of microcooling fins for microelectronics applications. The various types of cooling fins have been fabricated on the surface of a silicon wafer (4inch-N type) by using wet etching technique. The designed micro fins and micro channels are considered as an effective method for cooling microelectronics devices generating high heat flux. Further we extensively investigate the design processes fabricating micro fins and channels which can cool the heat generated from high density electronics devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.301-306
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• 2000

This paper describes on the fabrication of a SOI substrate by SDB technology and electrochemical etch-stop. The surface of the thinned SDB SOI substrate is more uniform than that of grinding or polishing by mechanical method, and this process was found to be a very accurate method for SOI thickness control. During electrochemical etch-stop, leakage current versus voltage curves were measured for analysis of the open current potential(OCP) point, the passivation potential(PP) point and anodic passivation potential. The surface roughness and the controlled thickness selectivity of the fabricated a SDB SOI substrate were evaluated by using AFM and SEM, respectively.

• Journal of Sensor Science and Technology
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• v.19 no.3
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• pp.209-213
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• 2010

This paper describes the fabrication and characteristics of AlN piezoelectric MPG(micro power generator). The micro energy harvester was fabricated to convert ambient vibration energy to electrical power as a AlN piezoelectric cantilever with Si proof-mass. To be compatible with CMOS process, AlN thin film was grown at low temperature by RF magnetron sputtering and micro power generators were fabricated by MEMS technologies. X-ray diffraction pattern proved that the grown AlN film had highly(002) orientation with low value of FWHM(full width at the half maximum, $\theta=0.276^{\circ}$) in the rocking curve around(002) reflections. The implemented harvester showed the $198.5\;{\mu}m$ highest membrane displacement and generated 6.4 nW of electrical power to $80\;k{\Omega}$ resistive load with $22.6\;mV_{rms}$ voltage from 1.0 G acceleration at its resonant frequency of 389 Hz. From these results, the AlN piezoelectric MPG will be possible to suitable with the batch process and confirm the possibility for power supply in portable, mobile and wearable microsystems.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.20 no.4
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• pp.106-112
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• 2021

Thermoplastic microfluidic devices are used in BioMEMS for medical and biotechnology applications, such as gene extraction, DNA analysis, and virus detection. In this research, a simple fabrication protocol with a commercially available pneumatic hot press is proposed and demonstrated for polycarbonate microfluidic devices. Microfluidic channels with a width of 200 ㎛ and a height of 10 ㎛ were designed and machined onto a brass plate as a mold insert using a CNC milling machine. The resulting microfluidic channels on the mold insert were assessed and found to have an actual width of 198 ㎛ and a height of 10 ± 0.25 ㎛. The microfluidic channels were replicated on a polycarbonate sheet using the proposed replication technique at 146℃ for 20 minutes under a constant load of 2400 kgf. The devices were then naturally cooled to 100℃ while maintaining the same pressure. It was found that the microchannels were successfully replicated in the polycarbonate, with a width of 198 ㎛ and a height of 10.07 ㎛. The proposed replication technique thus offers the rapid mass production of high-quality microfluidic devices at a low cost with a process that, unlike conventional photolithography systems, does not require expensive equipment.

• Journal of the Semiconductor & Display Technology
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• v.19 no.2
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• pp.77-81
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• 2020

Silicon wafer etching in micro electro mechanical systems (MEMS) fabrication is challenging to form 3-D structures. Well known Si-wet etch of silicon employs potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH) and sodium hydroxide (NaOH). However, the existing silicon wet etching process has a fatal disadvantage that etching of the back side of the wafer is hard to avoid. In this study, a wet etching bath for 150 mm wafers was designed to prevent back-side etching of silicon wafer, and we demonstrated the optimized process recipe to have anisotropic wet etching of silicon wafer without any damage on the backside. We also presented the design of wet bath for 300 mm wafer processing as a promising process development.