• Journal of Korean Society of Forest Science
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• v.105 no.2
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• pp.186-192
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• 2016

This study was conducted to develop microsatellite markers in Quercus variabilis using next generation sequencing. A total of 305,771 reads (384 bp on average) were generated on a Roche GS-FLX system, yielding 117 Mbp of sequences. The de novo assembly resulted in 7,346 contigs. A total of 606 contigs (20.75%) including 911 microsatellite loci were derived from the 2,921 contigs longer than 500 bp. A total of 180 primer sets were designed from the 911 microsatellite loci and screened in eight Q. variabilis individual trees sampled from a natural stand to obtain polymorphic loci. As a result, a total of thirteen polymorphic microsatellite loci were selected and used for estimating population genetic parameters in the 54 individual trees. The mean number of effective alleles was 4.996 ranging from 2.439 to 7.515. The observed heterozygosity and the expected heterozygosity ranged between 0.731 and 1.000 with an average of 0.873 and from 0.590 to 0.867 with an average of 0.766, respectively. Null alleles were not detected in all loci. No significant linkage disequilibrium was detected after Bonferroni correction in all loci. In the near future, these novel polymorphic microsatellite markers will be used to study population and conservation genetics of Q. variabilis of Korea in more detail.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.21-34
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• 2002

In this paper we propos a new hardware architecture of modular exponentiation using a division chain method which has been proposed in (2). Modular exponentiation using the division chain is performed by receding an exponent E as a mixed form of multiplication and addition with divisors d=2 or $d=2^I +1$ and respective remainders r. This calculates the modular exponentiation in about $1.4log_2$E multiplications on average which is much less iterations than $2log_2$E of conventional Binary Method. We designed a linear systolic array multiplier with pipelining and used a horizontal projection on its data dependence graph. So, for k-bit key, two k-bit data frames can be inputted simultaneously and two modular multipliers, each consisting of k/2+3 PE(Processing Element)s, can operate in parallel to accomplish 100% throughput. We propose a new encoding scheme to represent divisors and remainders of the division chain to keep regularity of the data path. When it is synthesized to ASIC using Samsung 0.5 um CMOS standard cell library, the critical path delay is 4.24ns, and resulting performance is estimated to be abort 140 Kbps for a 1024-bit data frame at 200Mhz clock In decryption process, the speed can be enhanced to 560kbps by using CRT(Chinese Remainder Theorem). Futhermore, to satisfy real time requirements we can choose small public exponent E, such as 3,17 or $2^{16} +1$, in encryption and verification process. in which case the performance can reach 7.3Mbps.

• Korean Journal of Fisheries and Aquatic Sciences
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• v.48 no.2
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• pp.151-157
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• 2015

This study was conducted to evaluate the effect of lactic acid bacterial fermentation on the antioxidant and anti-inflammatory activity of an edible brown alga, Eisenia bicyclis. Lactic acid bacteria were inoculated into and cultivated in E. bicyclis water extract. The antioxidant activity of the extract was assayed before and following fermentation. Antioxidant activity was determined by assaying the levels of radical scavenging activity against 2,2'-diphenyl-1-picrylhydrazyl (DPPH), hydroxyl radical and alkyl radical. The lactic acid bacterial fermentation of E. bicyclis extract resulted in enhanced antioxidant activity. The greatest enhancement of antioxidant activity was seen in the DPPH radical scavenging assay, in which E. bicyclis extract was fermented by Pediococcus pentosaceus MBP-34 strain for 12 h. This fermented extract also exhibited higher inhibitory activity (96.66%) on nitric oxide production compared with other lactic acid bacterial fermented extracts or raw extract (189.60%). In conclusion, fermentation by bacterial strain is an attractive strategy for developing value-added food ingredients.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.363-371
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• 2013

This paper describes a multi-standard LDPC decoder which supports 19 block lengths(576~2304) and 6 code rates(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6) of IEEE 802.16e mobile WiMAX standard and 3 block lengths(648, 1296, 1944) and 4 code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A DFU(decoding function unit) based on sign-magnitude arithmetic is used for hardware reduction. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.13-${\mu}m$ CMOS cell library. It has 312,000 gates and 70,000 bits RAM. The estimated throughput is about 79~210 Mbps at 100 MHz@1.8v.

• Korean Journal of Microbiology
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• v.54 no.3
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• pp.280-282
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• 2018

Pseudoalteromonas sp. meg-B1 belonging to Gammaproteobacteria was isolated from marine sediment in Jeju island. Here, we report the draft genome sequence of strain meg-B1 with a size of approximately 4.15 Mbp and a mean G + C content of 41.2%. The draft genome included 3,606 coding sequences, and 9 ribosomal RNA and 94 transfer RNA genes. In the draft genome, genes (e.g. choline dehydrogenase) involved in the accumulation of compatible solutes required for survival in marine environments have been identified.

• KSBB Journal
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• v.11 no.2
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• pp.165-172
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• 1996

To obtain a correctly folded human proinsulin, export of proinsulin using Staphylococcal protein A signal sequence-mediated secretion pathway has been attempted in E.coli. A secretion operon for proinsulin was constructed by consecutively connecting T7 promoter, SPA ribosome binding site, SPA signal sequence gene, and human proinsulin gene. Little immunoreactive proinsulin was detected in the periplasmic space and. culture medium, and not even in cytoplasmic space. The qualitative analysis of transcribed proinsulin mRNA and the in vitro transcription/translation experiment suggests that the negligible level of proinsulin export appears to be due to intracellular degradation of proinsulin, rather than due to the blockage during translocation. However, expression of proinsulin fusion protein such as MBP-proinsulin could dramatically increase export of proinsulin in E.coli.

• The Bulletin of The Korean Astronomical Society
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• v.40 no.2
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• pp.29.3-30
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• 2015

We introduce an advanced one-to-one galaxy correspondence method that populates dark matter halos with galaxies by tracing merging histories of most bound member particles (MBPs) identified in simulated virialized halos. To estimate the survival time of a satellite galaxy, we adopt several models of tidal-destruction time derived from an analytic calculation, isolated galaxy simulations, and cosmological simulations. We build mock galaxy samples for each model by using a merging tree information of MBPs from our new Horizon Run 4 N-body simulation from z = 12 to 0. For models of galaxy survival time derived from cosmological and isolated galaxy simulations, about 40% of satellites galaxies merged into a certain halo are survived until z = 0. We compare mock galaxy samples from our MBP-galaxy correspondence scheme and the subhalo-galaxy scheme with SDSS volume-limited galaxy samples around z = 0 with $M_r-5{\log}h$ < -21 and -20. Compared to the subhalo-galaxy correspondence method, our method predicts more satellite galaxies close to their host halo center and larger pairwise peculiar velocity of galaxies. As a result, our method reproduces the observed galaxy group mass function, the number of member galaxies, and the two-point correlation functions while the subhalo-galaxy correspondence method underestimates them.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.6
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• pp.1056-1063
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• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decoder is parameterized for the code rates 1/2, 1/3 and constraint lengths 7,9, thus it has four operation nodes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency. Also, the simulation results for BER (Bit Error Rate) performance show that the Viterbi decoder has BER of $10^{-4}$ at $E_b/N_o$ of 3.6 dB when it operates with code rate 1/3 and constraints 7.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.4
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• pp.123-134
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• 2004

In this paper a high speed architecture of the RC4 stream cipher is proposed and its FPGA implementation is presented. Compared to the conventional RC4 designs which have long initialization operation or use double or triple S-arrays to reduce latency delay due to S-array initialization phase, the proposed architecture for RC4 stream cipher eliminates the S-array initialization operation using 256-bit valid entry scheme and supports 40/128-bit key lengths with efficient modular arithmetic hardware. The proposed RC4 stream cipher is implemented using Xilinx XCV1000E-6H240C FPGA device. The designed RC4 stream cipher has about a throughput of 106 Mbits/sec at 40 MHz clock and thus can be applicable to WEP processor and RC4 key search processor.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.18-26
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• 1999

This paper presents the architecture and design of a DSSS MODEM ASIC chip for wireless local area networks (WLAN). The implemented MODEM chip supports the DSSS physical layer specifications of the IEEE 802.11. The chip consits of a transmitter and a receiver which contain a CRC encoder/decoder, a differential encoder/decoder, a frequency offset compensator and a timing recovery circuit. The chip supports various data rates, i.e., 4,2 and 1Mbps and provides both DBPSK and DQPSK for data modulation. We have performed logic synthesis using the $SAMSUNG^{TM}$ $0.6{\mu}m$ gate array library and the implemented chip consists of 53,355 gates. The MODEM chip operates at 44MHz, the package type is 100-pin QFP and the power consumption is 1.2watt at 44MHz. The implemented MODEM architecture shows lower BER compared with the Harris HSP3824.