• Journal of the Institute of Electronics Engineers of Korea CI
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• v.49 no.3
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• pp.8-14
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• 2012

Improving the speed of image processing is in great demand according to spread of high quality visual media or massive image applications such as 3D TV or movies, AR(Augmented reality). SIMD computer attached to a host computer can accelerate various image processing and massive data operations. MAMS is a multi-access memory system which is, along with multiple processing elements(PEs), adequate for establishing a high performance pipelined SIMD machine. MAMS supports simultaneous access to pq data elements within a horizontal, a vertical, or a block subarray with a constant interval in an arbitrary position in an $M{\times}N$ array of data elements, where the number of memory modules(MMs), m, is a prime number greater than pq. MAMS-PP4 is the first realization of the MAMS architecture, which consists of four PEs in a single chip and five MMs. This paper presents implementation of image processing algorithms and performance analysis for MAMS-PP16 which consists of 16 PEs with 17 MMs in an extension or the prior work, MAMS-PP4. The newly designed MAMS-PP16 has a 64 bit instruction format and application specific instruction set. The author develops a simulator of the MAMS-PP16 system, which implemented algorithms can be executed on. Performance analysis has done with this simulator executing implemented algorithms of processing images. The result of performance analysis verifies consistent response of MAMS-PP16 through the pyramid operation in image processing algorithms comparing with a Pentium-based serial processor. Executing the pyramid operation in MAMS-PP16 results in consistent response of processing time while randomly response time in a serial processor.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.6
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• pp.55-64
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• 2017

High-capacity, high-definition image applications need to process considerable amounts of data at high speed. Accordingly, users of these applications demand a high-speed parallel execution system. To increase the speed of a parallel execution system, Park (2004) proposed a technique, called MAMS (Multi-Access Memory System), to access data in several execution units without the conflict of parallel processing memories. Since then, many studies on MAMS have been conducted, furthering the technique to MAMS-PP16 and MAMS-PP64, among others. As a memory architecture for parallel processing, MAMS must be constructed in one chip; therefore, a method to achieve the identical functionality as the existing MAMS while minimizing the architecture needs to be studied. This study proposes a method of miniaturizing the MAMS architecture in which the architectures of the ACR (Address Calculation and Routing) circuit and MMS (Memory Module Selection) circuit, which deliver data in memories to parallel execution units (PEs), do not use the MMS circuit, but are constructed as one shift and conditional statements whose number is the same as that of memory modules inside the ACR circuit. To verify the performance of the realized architecture, the study conducted the processing time of the proposed MAMS-PP64 through an image correlation test, the results of which demonstrated that the ratio of the image correlation from the proposed architecture was improved by 1.05 on average.

• Journal of the Korea Society of Computer and Information
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• v.21 no.12
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• pp.81-89
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• 2016

In this paper, we design and implement a mouse movement measurement system using an infrared sensor called MAMS (Mouse Activity Measurement System). Unlike existing systems, MAMS can measure movements between IREDs. MAMS is removable allowing convenient portability and is also low cost. MAMS automatically measures mouse activity during a pre-set time interval. Since the measured data can be easily stored in a computer system, it is much simpler and more efficient than the Ugo 47420 model. Moreover, MAMS can be used in medical and veterinary field to eliminate manual observations.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.4
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• pp.119-128
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• 2019

Due to the nature of the 3D graphics processor system, many mathematical calculations are required and parallel processing research using GPU (Graphics Processing Unit) is being performed for high-speed processing. In this paper, we propose a 3D graphics processor using MAMS, a parallel processor that does not use cache memory, to solve the GPU problem of increasing bandwidth caused by cache memory miss and the problem that 3D shader processing speed is not constant. The 3D graphics processor using MAMS proposed in this paper designed Vertex shader, Pixel shader, Tiling and Rasterizing structure using DirectX command analysis, the FPGA(Xilinx Virtex6@100MHz) board for MAMS was constructed and designed using Verilog. We compared the processing time of the developed FPGA (100Mhz) and nVidia GeForce GTX 660 (980Mhz), the processing time using GTX 660 was not constant and suing MAMS was constant.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.149-151
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• 2002

We had been developing the variety of parallel processing systems in order to improve the processing speed of visual media applications. These systems were using multi-access memory system(MAMS) as a parallel memory system, which provides the capability of the simultaneous accesses of image points in a line-segment with an arbitrary degree, which is required in many low-level image processing operations such as edge or line detection in a particular direction, and so on. But, the performance of these systems did not give a faithful speed because of asynchronous feature between MAMS and processing elements. To improve the processing speed of these systems, we have been investigated a pipelined parallel processing system using MAMS. Although the system is considered as being the single instruction multiple data(SIMD) type like the early developed systems, the performance of the system yielded about 2.5 times faster speed.

• Journal of Korea Multimedia Society
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• v.16 no.8
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• pp.914-926
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• 2013

Among the recent security systems, security system with fingerprint recognition gets many people's interests through the strengths such as exclusiveness, convenience, etc, in comparison with other security systems. The most important matters for fingerprint recognition system are reliability of matching between the fingerprint in database and user's fingerprint and rapid process of image processing algorithms used for fingerprint recognition. The existing fingerprint recognition system reduces the processing time by removing some processes in the feature extraction algorithms but has weakness of a reliability. This paper realizes the fingerprint recognition algorithm using MAMS(Multi-Access Memory System) for both the rapid processing time and the reliability in feature extraction and matching accuracy. Reliability of this process is verified by the correlation between serial processor's results and MAMS-PP64's results. The performance of the method using MAMS-PP64 is 1.56 times faster than compared serial processor.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.5
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• pp.97-103
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• 2010

There are many algorithms for 2D to 3D graphic conversion technology which have the high complexity and large scale of iterative computation. So in this paper propose parallel algorithm and high speed graphics accelerator architecture using Park's MAMS(Multiple Access Memory System) for Phong Shading, one of many 3D algorithms. The Proposed SIMD processor architecture is simulated by HDL and simulated and got 30 times faster result. It means any kinds of 3D algorithm can make parallel algorithm and accelerated by SIMD processor with Park's MAMS for real time processing.

• Journal of Korea Multimedia Society
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• v.14 no.11
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• pp.1401-1408
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• 2011

This dissertation present a chip with Multi-Access Memory System(MAMS) and parallel processor for 16 Processing Elements of image processing purpose. MAMS is a kind of parallel access memory system and can simultaneously access to random pixel datas with eight types. It is possible to set a interval about pixel datas to access, too. The parallel processor built-in MAMS actually has been realized in 2003 but its performance fell short of a real time process for high-definition images. I designed a improved parallel processing system by means of addition and expansion of Memory Modules and Processing Elements of previous one. It is feasible to perform a Morphological Closing at the speed of 3 times of the previous one and 6 times of serial system.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04b
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• pp.247-249
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• 2004

마이크로어레이 기술은 근래에 개발된 신기술로써 동시에 수천-수만 개의 유전자 발현을 측정할 수 있어 다양한 생물학적 연구에 이용되고 있다. 여러 단계의 실험 과정과 이를 통해 얻은 다량의 데이터를 처리하기 위해서는 이를 효율적으로 관리. 저장, 분석할 수 있는 통할 정보 관리 시스템을 필요로 한다. 현재 외국에서는 몇몇 관리시스템이 개발되어 있고. 국내에서도 WEMA 등이 있지만 아직 데이터 관리부분에 기능이 치우쳐 있다. 따라서 우리는 복잡한 자료구조를 가지는 마이크로어레이의 실험 정보와 각 단계별 처리 정보 등을 사용자의 관점에서 효과적이고 체계적으로 관리할 수 있고, 데이터 정규화 및 다양한 통계적 분석 기능을 갖춰 불필요한 시간과 비용을 줄임으로써 마이크로어레이 연구에 도움을 주고자 통합 분석관리 시스템 cMAMS (cDNA Microarray Analysis and Management System)를 개발하였다. 웹 기반으로 구현된 cMAMS는 데이터를 저장, 관리하는 부분과 데이터를 분석하는 부분, 그리고 모든 관련 점보가 저장되는 데이터베이스 부분으로 구성되어 있다 데이터관리부분에서는 WEMA의 계층적 데이터구조론 도입해 관리의 효율성을 높이고 시스템의 이용자를 시스템운영자, 프로젝트관리자, 일반사용자로 구분하여 데이터 접근을 제한함으로써 보안성을 높였다. 통계처리 언어 R로 구현된 데이터분석 부분은 7 단계의 다양한 분석(전처리 정규화, 가시화, 군집분석. 판별분석, 특이적 발현 유전자 선뿐, 마이크로어레이 간의 상판분석)이 가능하도록 구현하였고, 분석결과는 데이터베이스에 저장되어 추후에 검토 및 연구자간의 공유가 가능하도록 하였다. 데이터베이스는 실험정보가 저장된 데이터베이스, 분석결과가 저장된 데이터베이스, 그리고 유전자 정보 탐색을 위한 데이터베이스로 분류해 데이터를 효율적으로 관리할 수 있게 하였다. 본 시스템은 LiNUX를 운영체계로 하고 데이터베이스는 MYSQL로 하여 JSP, Perl. 통계처리 언어인 R로 구현되었다.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.429-432
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• 2000

The new MPEG-4 video coding standard enables content-based functionalities. In order to support the philosophy of the MPEG-4 visual standard, each frame of video sequences should be represented in terms of video object planes (VOP’s). In other words, video objects to be encoded in still pictures or video sequences should be prepared before the encoding process starts. Therefore, it requires a prior decomposition of sequences into VOP’s so that each VOP represents a moving object. A parallel processing system is required an automatic segmentation to be processed in real-time, because an automatic segmentation is time consuming. This paper addresses the parallel processing: system for an automatic segmentation for separating moving object from the background in image sequences. The proposed parallel processing system comprises of processing elements (PE’s) and a multi-access memory system (MAMS). Multi-access memory system is a memory controller to perform parallel memory access with the variety of types: horizontal, vertical, and block access way. In order to realize these ways, a multi-access memory system consists of a memory module selection module, data routing modules, and an address calculation and routing module. The proposed system is simulated and evaluated by the CADENCE Verilog-XL hardware simulation package.