• Title/Summary/Keyword: M&V 적용

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Development of a Rapid Enrichment Broth for Vibrio parahaemolyticus Using a Predictive Model of Microbial Growth with Response Surface Analysis (미생물 생장 예측모델과 반응표면분석법을 이용한 Vibrio parahaemolyticus의 신속 증균배지 개발)

  • Yeon-Hee Seo;So-Young Lee;Unji Kim;Se-Wook Oh
    • Journal of Food Hygiene and Safety
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    • v.38 no.6
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    • pp.449-456
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    • 2023
  • In this study, we developed Rapid Enrichment Broth for Vibrio parahaemolyticus (REB-V), a broth capable enriching V. parahaemolyticus from 100 CFU/mL to 106 CFU/mL within 6 hours, which greatly facilitates the rapid detection of V. parahaemolyticus. Using a modified Gompertz model and response surface methodology, we optimized supplement sources to rapidly enrich V. parahaemolyticus. The addition of 0.003 g/10 mL of D-(+)-mannose, 0.002 g/10 mL of L-valine, and 0.002 g/10 mL of magnesium sulfate to 2% (w/v) NaCl BPW was the most effective combination of V. parahaemolyticus enrichment. Optimal V. parahaemolyticus culture conditions using REB-V were at pH 7.84 and 37℃. To confirm REB-V culture efficiency compared to 2% (w/v) NaCl BPW, we assessed the amount of enrichment achieved in 7 hours in each medium and extracted DNA samples from each culture every hour. Real-time PCR was performed using the extracted DNA to verify the applicability of this REB-V culture method to molecular diagnosis. V. parahaemolyticus was enriched to 5.452±0.151 Log CFU/mL in 2% (w/v) NaCl BPW in 7 hours, while in REB-V, it reached 7.831±0.323 Log CFU/mL. This confirmed that REB-V enriched V. parahaemolyticus to more than 106 CFU/mL within 6 hours. The enrichment rate of REB-V was faster than that of 2% (w/v) NaCl BPW, and the amount of enrichment within the same time was greater than that of 2% (w/v) NaCl BPW, indicating that REB-V exhibits excellent enrichment efficiency.

Development and its Characteristics of the 40kV x-ray transmission anode target tube (40kV용 투과 양극형 x-ray tube의 개발 및 특성분석)

  • Kim, Sung-Soo;Kim, Do-Yun
    • Journal of the Korean Vacuum Society
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    • v.17 no.3
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    • pp.234-239
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    • 2008
  • Tungsten and rhodium target tube for a 40 kV x-ray transmission anode was developed to apply to the hand-held XRF(X-Ray Fluorescence) apparatus and its characteristics were evaluated. From the measurement of the energy distribution and dose of x-ray, it was confirmed that our results were good agreements with the known ones. The optimum thickness of metal film deposited on Be window to extract the maximum dose were $2.6{\mu}m$ and $2.7{\mu}m$ in case of W-target tube and Rh-target tube, respectively. When it was continuously worked during 30 min. at 40 kV in tube voltage and at $60{\mu}A$ in tube current, the temperature at target did not exceed $50^{\circ}C$. Our results reveals that the 40 kV x-ray transmission anode tube can be applied to the hand-held XRF apparatus.

Evaluation of Extremely Low Frequency Magnetic Fields emission Level from High Voltage Transmission Lines (고압 송전선로에서 극저주파 자기장 영향평가 적용에 관한 연구)

  • Jung, Joon Sig;Choi, Sung Ho;Jeon, Hyung Jin;Kim, Yoon Shin;Hong, Seung Cheol
    • Journal of Environmental Impact Assessment
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    • v.23 no.5
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    • pp.353-363
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    • 2014
  • The purpose of this study was to investigated the ELF-MF emission level of various environments such as 258 facilities near located to high voltage transmission lines and 120 high voltage transmission lines, 17 underground cable lines. In addition, ELF-MF reduction rate according to separation distance was calculated by using simulations. An appropriate separation distance showing below 4mG was at least 70m. In the case of the appropriate separation distance for 120 high voltage transmission lines, 154kV required 20m of separation distance and 345kV required 60m of separation distance. The simulation results showed that the appropriate separation distance showing below 4mG was 40m and 60m for overhead 154kV and 345kV respectively. To adjust the worst conditions considering the aspects of environmental impact assessment study and the electric power currents that will increase in the future, the appropriate minimum separation distance for HVTL is judged to be above 70m in this study. Thus, there is a need to establish the greenbelt or buffer zone within 70m so as to create an environment in which the receptors are not exposed and thereby eliminate the risk factors of ELF-MF against humans.

A Integrated Circuit Design of DC-DC Converter for Flat Panel Display (플랫 판넬표시장치용 DC-DC 컨버터 집적회로의 설계)

  • Lee, Jun-Sung
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.10
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    • pp.231-238
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    • 2013
  • This paper describes a DC-DC converter IC for Flat Panel Displays. In case of operate LCD devices various type of DC supply voltage is needed. This device can convert DC voltage from 6~14[V] single supply to -5[V], 15[V], 23[V], and 3.3[V] DC supplies. In order to meet current and voltage specification considered different type of DC-DC converter circuits. In this work a negative charge pump DC-DC converter(-5V), a positive charge pump DC-DC converter(15V), a switching Type Boost DC-DC converter(23V) and a buck DC-DC converter(3.3V). And a oscillator, a thermal shut down circuit, level shift circuits, a bandgap reference circuits are designed. This device has been designed in a 0.35[${\mu}m$] triple-well, double poly, double metal 30[V] CMOS process. The designed circuit is simulated and this one chip product could be applicable for flat panel displays.

A Class-C type Wideband Current-Reuse VCO With 2-Step Auto Amplitude Calibration(AAC) Loop (2 단계 자동 진폭 캘리브레이션 기법을 적용한 넓은 튜닝 범위를 갖는 클래스-C 타입 전류 재사용 전압제어발진기 설계)

  • Kim, Dongyoung;Choi, Jinwook;Lee, Dongsoo;Lee, Kang-Yoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.11
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    • pp.94-100
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    • 2014
  • In this paper, a design of low power Current-Reuse Voltage Controlled Oscillator (VCO) which has wide tuning range about 1.95 GHz ~ 3.15 GHz is presented. Class-C type is applied to improve phase noise and 2-Step Auto Amplitude Calibration (AAC) is used for minimizing the imbalance of differential VCO output voltage which is main issue of Current-Reuse VCO. The mismatch of differential VCO output voltage is presented about 1.5mV ~ 4.5mV. This mismatch is within 0.6 % compared with VCO output voltage. Proposed Current-Reuse VCO is designed using CMOS $0.13{\mu}m$ process. Supply voltage is 1.2 V and current consumption is 2.6 mA at center frequency. The phase noise is -116.267 dBc/Hz at 2.3GHz VCO frequency at 1MHz offset. The layout size is $720{\times}580{\mu}m^2$.

3kpc 내 은하평면의 성간소광법칙

  • Seong, Hwan-Gyeong;Bessell, M.S.
    • The Bulletin of The Korean Astronomical Society
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    • v.38 no.1
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    • pp.57.1-57.1
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    • 2013
  • Non-LTE 항성대기모형인 Tlusty 모형의 합성색지수와 성간소광을 매우 적게 받은 산개성단에 있는 별들의 색지수를 바탕으로 O와 B형 별의 고유색지수 관계를 채택하였다. 태양인근 3kpc 내에 있는 약 190개 젊은 산개성단의 가시광 및 근적외선 2MASS JHKs 관측자료와 위에서 채택한 고유 색지수 관계를 적용하여 색 초과비 E(V-I)/E(B-V), E(V-J)/E(B-V), E(V-H)/E(B-V), 및 E(V-Ks)/E(B-V)를 얻고, 색 초과비와 $R_V$의 관계를 사용하여, 각 성단의 성간소광법칙 $R_V$를 결정하였다. 국부 나선팔의 백조자리 방향과 Per 나선팔에 있는 산개성단들은 약간 작은 $R_V$를 보이며, 큰개자리 방향의 국부 나선팔에 있는 산개성단은 정상적인$R_V$를, 그리고 Sgr-Car 나선팔에 있는 산개성단들은 약간 큰 값을 보였다. 이 결과는 최대 편광도를 보이는 파장과 $R_V$의 관계로 얻을 수 있는 양상과 잘 일치한다.

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A Study on the Design of Amplifier for Source Driver IC applicable to the large TFT-LCD TV (대형 TFT-LCD TV에 적용 가능한 Source Driver IC 감마보정전압 구동용 앰프설계에 관한 연구)

  • Son, Sang-Hee
    • Journal of IKEEE
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    • v.14 no.2
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    • pp.51-57
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    • 2010
  • A CMOS rail-to-rail high voltage buffer amplifier is proposed to drive the gamma correction reference voltage of large TFT LCD panels. It is operating by a single supply and only shows current consumption of 0.5mA at 18V power supply voltage. The circuit is designed to drive the gamma correction voltage of 8-bit or 10-bit high resolution TFT LCD panels. The buffer has high slew rate, 0.5mA static current and 1k$\Omega$ resistive and capacitive load driving capability. Also, it offers wide supply range, offset voltages below 50mV at 5mA constant output current, and below 2.5mV input referred offset voltage. To achieve wide-swing input and output dynamic range, current mirrored n-channel differential amplifier, p-channel differential amplifier, a class-AB push-pull output stage and a input level detector using hysteresis comparator are applied. The proposed circuit is realized in a high voltage 0.18um 18V CMOS process technology for display driver IC. The circuit operates at supply voltages from 8V to 18V.

The Study of process for VV&A on acquiring the credibility of M&S (M&S 신뢰도 확보를 위한 VV&A 절차 적용에 관한 연구)

  • Choi, Yoo Jin
    • Journal of the Korean Society of Systems Engineering
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    • v.5 no.2
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    • pp.11-16
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    • 2009
  • This study introduces the verification, validation & accreditation (VV&A) process for modeling & simulation (M&S). VV&A is standard process for credibility of M&S. In several countries including USA, for weapon system of Defense Development using M&S, VV&A is necessary procedures to acquire official approving for credibility of M&S. Many countries have regular recommend practice guide (RPG) and instructive for VV&A of M&S. In this study, we focus the VV&A key concepts as Department of Defense RPG of USA and give the outline of the main VV&A concepts because we don't have any available VV&A Instructive. Also, this report documents the first significant VV&A application for a MITS(M-SAM Integrate Test System) including Verification and Validation(V&V) activity and tasks.

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A Design of CMOS Analog-Digital Converter for High-Speed . Low-power Applications (고속 . 저전력 CMOS 아날로그-디지탈 변환기 설계)

  • Lee, Seong-Dae;Hong, Guk-Tae;Jeong, Gang-Min
    • The Transactions of the Korea Information Processing Society
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    • v.2 no.1
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    • pp.66-74
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    • 1995
  • A 8-bit 15MHz CMOS subranging Analog-to-Digital converter for high-speed, low-power consumption applications is described. Subranging, 2 step flash, A/D converter used a new resistor string and a simple comparator architecture for the low power consumption and small chip area. Comparator exhibites 80dB loop gain, 50MHz conversion speed, 0.5mV offset and maximum error of voltage divider was 1mV. This Analog-to-Digital converter has been designed and fabricated in 1.2 m N-well CMOS technology. It consumed 150mW power at +5/-5V supply and delayed 65ns. The proposed Analog-to-Digital converter seems suitable for high- speed, low-power consumption, small area applications and one-chip mixed Analog- Digital system. Simulations are performed with PSPICE and a fabricated chip is tested.

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