• 전자공학회논문지SC
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• 제37권4호
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• pp.35-41
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• 2000

본 논문에서는 유한체 GF(2/sup m/)상에서 두 다항식의 승산 알고리즘을 제시하였다. 이 알고리즘은 반복적인 배열로 병렬 승산을 효과적으로 실현하며, 동일한 시간에 고속 동작을 실현한다. 제시된 승산기는 승산연산부와 mod연산부, 원시 기약다항식연산부로 구성하였다. 승산연산부는 멀티플렉서, X-OR게이트, AND게이트, MUX로 구성하였으며, mod연산부는 AND게이트, X-OR게이트로 구성하였다. 또한 본 논문에서 제시한 승산에는 효과적인 파이프형을 도입하였다. 도출된 모든 승산기는 고속 동작하며, 회로 복잡성이 감소한다. 셀들의 내부결선도는 VLSI 실현에 적합하도록 규칙적으로 구성되었다.

• Journal of Power Electronics
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• 제10권5호
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• pp.477-484
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• 2010

A pulse width modulation-voltage source inverter (PWM-VSI) is used for variable speed permanent magnet synchronous motor (PMSM) drives. The PWM-VSI fed PMSM has two major disadvantages. Firstly, the PWM-VSI DC-link voltage limits the magnitude of the PMSM terminal voltage. As a result, the motor speed is restricted. Secondly, in a low speed range, the PWM-VSI modulation index declines. This is caused by a high DC-link voltage and a low terminal voltage ratio. As a result, the distortion of the voltage command and the stator current are increased. This paper proposes an optimal pulse amplitude modulation (PAM) control which can adjust the inverter DC-link voltage by using a buck-boost DC-DC converter. At a low speed range, the proposed system can reduce the distortion of the voltage command, which improves the stator current waveform. Also, the allowable speed range is extended. In order to verify the proposed method, experimental results are provided to confirm the simulation results.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권3호
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• pp.176- 184
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• 2010

A low-power inductorless 1:4 DEMUX and a 4:1 MUX for a 90 nm CMOS are presented. The DEMUX can be operated at a speed of 25 Gb/s with the power supply voltage of 1.05 V, and the power consumption is 8.9 mW. The area of the DEMUX core is $29\;{\times}\;40\;{\mu}m^2$. The operation speed of the 4:1 MUX is 13 Gb/s at a power supply voltage of 1.2 V, and the power consumption is 4 mW. The area of the MUX core is $30\;{\times}\;18\;{\mu}m^2$. The MUX/DEMUX mainly consists of differential pseudo-NMOS. In these MUX/DEMUX circuits, logic swing is nearly rail-to-rail, and a low $V_{dd}$. The component circuit is more scalable than a CML circuit, which is commonly used in a high-performance MUX/DEMUX. These MUX/DEMUX circuits are compatible with conventional CMOS logic circuit, and it can be directly connected to CMOS logic gates without logic level conversion. Furthermore, the circuits are useful for core-to-core interconnection in the system LSI or chip-to-chip communication within a multi-chip module, because of its low power, small footprint, and reasonable operation speed.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.727-730
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• 2005

In this paper, we propose a new current sense amplifier for low-voltage, high-speed SRAM. As a supply voltage is reduced, a sensing delay is increased owing to reduced cell read current. It causes a low-speed operation in SRAM. To overcome this problem, we present a new current sense amplifier which consists of the current-mirror type circuit with feedback structure. For demonstration, a 0.8-V, 256-Kb SRAM incorporating the proposed current sense amplifier has been designed with $0.18-{\mu}m$ CMOS technology. The simulation results show 15.6ns of the sensing delay reduction in comparison with a previous current sense amplifier and 11.5ns of the sensing delay reduction in comparison with a voltage sense amplifier.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.707-710
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• 1998

This paper presents a new voltage down converter(VDC) for low power, high speed DRAM. This VDC Consists of RVG(Reference Voltage Generator) and Driver Circuit. And it is independent of temperature variation, and Supply Voltage. Using weak inversion region, this RVG dissipates low power. Internal Voltage Source of this VDC is stable in spite of high speed operation of memory array. This circuit is designed with a $0.65\mu\textrm{m}$ nwell CMOS technology. In HSPICE simulation results, Temperature dependency of this RVG is $20\muV/^{\circ}C,$ supply voltage dependency is $\pm0.17%,$ $VCC=3.3V\pm0.3V,$ and current dissipation is $5.22\muA.$ Internal voltage source bouncing of this VDC is smaller than conventional VDC.

• 한국기계가공학회지
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• 제5권2호
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• pp.10-15
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• 2006

An introduction to orthogonal cutting model by FEM is given, followed by a review of similar work. The cutting process is treated as quasi-static and strain rate insensitive, so the model is applicable only to low speed cutting operation. Chip separation is accomplished along a predefined cutting path by means of an element death procedure. Contact elements with friction capability are used to model the interaction between the tool and the workpiece. FEM results are compared with cutting experiments with low speed for brass, and good correlations are found.

• Journal of Electrical Engineering and Technology
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• 제9권4호
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• pp.1277-1282
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• 2014

Concentrated flux interior permanent magnet (CFIPM) motors have the advantage that their utilization of flux linkage is more efficient than that of general IPM motors and CFIPM motors are suitable for washing machine motors, which demand low-speed, high-torque specifications. However, low efficiency occurs in the low-speed high-torque mode considering the high-speed operation for spin mode. This paper proposes a magnet overhang structure between the rotor core that reduces leakage flux and improves efficiency for a CFIPM in wash mode. Optimization of the 3D design of magnet overhang structures is performed to improve the efficiency with the same quantity of permanent magnets. The validity of the optimal design is experimentally verified through the fabrication of prototypes.

• Journal of Power Electronics
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• 제16권1호
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• pp.1-8
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• 2016

Dead time is typically incorporated in voltage source inverter systems to prevent short circuit cases. However, dead time causes an error between the output voltage and reference voltage. Hence, voltage equation-based algorithms, such as motor parameter estimation and back electromotive force (EMF)-based sensorless algorithms, are prone to estimation errors. Several dead-time compensation methods have been developed to reduce output voltage errors. However, voltage errors are still common in zero current crossing areas, and an effect of the error is much worse in a low speed region. Therefore, employing voltage equation-based algorithms in low speed regions is difficult. This study analyzes the conventional dead-time compensation method and output voltage errors in low speed operation areas. A current shaping method that can reduce output voltage errors is also proposed. Experimental results prove that the proposed method reduces voltage errors and improves the accuracy of the parameter estimation method and the performance of the back EMF-based sensorless algorithm.

• 전력전자학회논문지
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• 제18권6호
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• pp.523-529
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• 2013

A sensorless speed control of a permanent magnet synchronous motor(PMSM) which utilizes MRAS based scheme to estimate rotor speed and position is presented. Considering an error between real and estimated rotor position values, a state equation of PMSM in the synchronous d-q reference frame is represented. A state equation of model system which uses estimated speed and nominal parameter values is expressed. To minimize the errors between the derivatives of d-q axis currents of real and model system, MRAS based adaptation mechanisms for the estimation of rotor speed and position are derived. On the other hand, for the acceleration stage of motor just before the sensorless operation, an acceleration scheme using only d-axis current control is proposed. To show the validity of the proposed scheme, experimental works are carried out and evaluated. During acceleration stage, the acceleration scheme using only d-axis current command shows good acceleration performance and controlled current level. For the sensorless operation, at low speed (5% of rated speed), a good performance is observed.

• 전기학회논문지P
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• 제65권4호
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• pp.298-302
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• 2016

Currently, logistics are in small quantities and in diverse forms, and the amounts are continuously increasing. Railway logistics however are losing their market share every year mainly due to low operation speed and loading time, which means the trucks are covering the most of the freights. In order to solve these situations, this paper proposed the high speed freight train as working multi-modality with other modes to make effective transshipment. The high speed freight train has maximum operation speed of 300km/h and electric power to run centralized power supply. There are large dual door system, bogie system covering fluctuating load of 15[ton], automatic loading device, ULD(unit load device) bed and ULD locking system in this freight rolling stock. We calculated the performance of powering and braking capacity for this train and proposed how many vehicles are composed of train set. The results in this paper can help to make a decision to define the technical specification of High-speed freight train for the efficiency of rail freight service.