• Journal of Electrical Engineering and Technology
• /
• v.10 no.4
• /
• pp.1655-1666
• /
• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.4 no.4
• /
• pp.263-268
• /
• 2004

In this paper, we motivate the post-mask performance enhancement technique combined with the Multi-Threshold Voltage CMOS (MTCMOS) leakage current suppression technology, and integrate the new design issues related to the MTCMOS technology into the ASIC design methodology. The issues include short-circuit current and sneak leakage current prevention. Towards validating the proposed techniques, a Personal Digital Assistant (PDA) processor has been implemented using the methodology, and a 0.18um process. The fabricated PDA processor operates at 333MHz which has been improved about 23% at no additional cost of redesign and masks, and consumes about 2uW of standby mode leakage power which could have been three orders of magnitude larger if the MTCMOS technology was not applied.

• ETRI Journal
• /
• v.30 no.1
• /
• pp.113-128
• /
• 2008

Turbo codes are extensively used in current communications standards and have a promising outlook for future generations. The advantages of software defined radio, especially dynamic reconfiguration, make it very attractive in this multi-standard scenario. However, the complex and power consuming implementation of the maximum a posteriori (MAP) algorithm, employed by turbo decoders, sets hurdles to this goal. This work introduces an ASIP architecture for the MAP algorithm, based on a dual-clustered VLIW processor. It displays the good performance of application specific designs along with the versatility of processors, which makes it compliant with leading edge standards. The machine deals with multi-operand instructions in an innovative way, the fetching and assertion of data is serialized and the addressing is automatized and transparent for the programmer. The performance-area trade-off of the proposed architecture achieves a throughput of 8 cycles per symbol with very low power dissipation.

• Journal of Power Electronics
• /
• v.9 no.3
• /
• pp.410-417
• /
• 2009

This paper represents a design and implementation of a digital controller for a multi-phase synchronous buck converter (SBC) using a digital signal processor (DSP). The multi-phase SBC has generally been used for a voltage regulation module (VRM) of a microprocessor because of its high current handling capability at a low output voltage. The VRM requires high control performance of tight output regulation, high slew rate, and load sharing capability of multiple converters. In order to achieve these requirements, the design and implementation of a digital control system for a multi-phase SBC are presented in this paper. The digital PWM generation, current sensing, and voltage and current controller using a DSP TMS320F2812 are considered. The experimental results are provided to show the validity of the implemented digital control system.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.22 no.10
• /
• pp.2136-2149
• /
• 1997

This paper describes RISC core that has been designed for embedded and protable applications such as PDA or PCS. This RISC processor offers low power consumption and fast context switching. Processor performance is improved by using conditional instruction execution, block data transfer instruction, and multiplication instruction. This architecture is based on RISC principles. The processor adopts 3-stage instruction execution pipeline and has achieved single cycle execution using a 2-phase 40MHz clock. This results in a high instruction throughput and real-time interrupt response. This chip is implemented with $0.6{\mu}m$ triple metal CMOS technology and consists of about 88K transistors. The estimated power dissipation is 179mW.

• Proceedings of the Korean Institute of Communication Sciences Conference
• /
• 2004.07a
• /
• pp.335-335
• /
• 2004

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.17 no.6
• /
• pp.161-167
• /
• 2017

Recently, small radar has been reduced in size and power consumption to cope with various operating environments. It also requires the development of a small millimeter wave radar with high range resolution to disable the system of target with a single strike. In this paper, we design and implement a signal processor that can be used in small millimeter wave radar. The signal processor for the small millmeter wave radar is designed with a digital IF(Intermediate Frequency) receiver and DFT(Discrete Fourier Transform) module capable of real time FFT operation for miniaturization and low power consumption. Also it was to leverage the FPGA(Field Programmable Gate Array) and DAC(Digital Analog Converter) as a means for correcting the distortion of signals that can occur in the receive path of the small millimeter wave radar to create a RF signal that is used by the system. Finally, we verified the signal processor presented through performance test

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.12C
• /
• pp.1617-1622
• /
• 2004

MPEG/Audio decoder for mobile multimedia systems requires low power consumption. Implementations of AV decoder using a single RISC processor often need high power consumption owing to cash-miss in case of insufficient cash memory. In this paper, we present a MPEG/Audio decoder for mobile handset applications and implement it on a RISC processor embedding a minimized DSP accelerator. Audio decoding algorithm is splined into two parts; computation intensive and control intensive parts. Those parts we, respectively, allocated to DSP and RISC core, which are designed to run in parallel to increase the processing efficiency. The proposed system implements MP3 and AAC decoders at l7MHz and 24MHz clocks, which are reductions of 48% and 40% of complexities in comparison with implementations on a single RISC processor. The proposed method is adequate for mobile multimedia applications with insufficient cash memory.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.26 no.10
• /
• pp.1617-1623
• /
• 1989

The introduction of the fast Fourier transform(FFT),an efficient computational algorithm for the discrete Fourier transform(DFT) by Cooley and Tukey(1965), has brought to the limelight various other discrete transforms. Some of the analog functions from which these transforms have been derived date back to the early 1920's, for example, Walsh functions (Walsh, 1923) and Hadamard Transform(Enomoto et al, 1965). Fast algorithms developed for the forward transform are equally applicable, exept for minor changes, to the inverse transform. In this paper, we present a simple pipelined Hadamard matrix(HM) which is used to develop a fast algorithm for the Hadamard Processor (HP). The Fast Hadamard Transform(FHT) can be derived using matrix partitioning techniques. The HP system is incorporated through a modular design which permits tailoring to meet a wide range of video data link applications. Emphasis has been placed on a low cost, a low power design suitable for airbone system and video codec.

• Journal of the Korea Society of Computer and Information
• /
• v.16 no.1
• /
• pp.1-9
• /
• 2011

Recently, as mobile multimedia devices are used more and more, the needs for high-performance and low-energy multimedia processors are increasing. Application-specific integrated circuits (ASIC) can meet the needed high performance for mobile multimedia, but they provide limited, if any, generality needed for various application requirements. DSP based systems can used for various types of applications due to their generality, but they require higher cost and energy consumption as well as less performance than ASICs. To solve this problem, this paper proposes a single instruction multiple data (SIMD) based many-core processor which supports high-performance and low-power image data processing while keeping generality. The proposed SIMD based many-core processor composed of 16 processing elements (PEs) exploits large data parallelism inherent in image data processing. Experimental results indicate that the proposed SIMD-based many-core processor higher performance (22 times better), energy efficiency (7 times better), and area efficiency (3 times better) than conversional commercial high-performance processors.