• Proceedings of the KIEE Conference
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• 1995.07a
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• pp.237-239
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• 1995

The inverter for UPS system is required to satisfy pure sinusoidal output voltage with very low THD(Total Harmonic distortion). This paper proposes a TMS320c31 digital signal processor based predictive instantaneous control scheme of inverter. The proposed scheme is able to satisfy the conditions; high capability, high efficiency, low audible noise and robustness of inverter. The transient state characteristics of proposed inverter has been improved. in case of power failure or recovery, nonlinear load, sudden load change or parameters variations. Finally, the performance of the proposed inverter is shown and discussed by simulation and experiment.

• Proceedings of the KIEE Conference
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• 2004.05a
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• pp.150-152
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• 2004

The battery charge/discharge process, the final step of the secondary battery production process, requires real-time precision controls for improving both lifetime and performance of the battery cell. In this paper, we present embedded system design for precision control of the secondary battery charge/discharge production process using low power embedded processor based on embedded linux. This system receive charge/discharge command from the main server through ethernet. Compared to existing charge/discharge control system, our design makes low cost and precision control system possible.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.157-159
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• 2014

In this paper, we introduce SlimSRP, an ultra-low-power digital signal processor (DSP) solution for mobile audio and voice applications. So far, application processors (APs) have taken charge of all the tasks in mobile devices. However, they have suffered from short battery life problems to deal with complex usage scenarios, such as always-on voice trigger with continuous audio playback. From extensive analysis of audio and voice application characteristics, SlimSRP is designed to relive the performance and power burden of APs. It employs three-issue VLIW architecture, and the major low-power and high-performance techniques include: (1) an optimized register-file architecture friendly for constants generation, (2) a powerful instruction set to reduce the number of register file accesses and (3) a unique instruction compression scheme that contributes to saved memory size and reduced cache miss. An implementation of SlimSRP runs at up to 200MHz and the logic occupies 95K NAND2 gates in Samsung 28LPP process. The experimental results demonstrate that a MP3 decoder application with a 128kbps 44.1kHz input can run at 5.1MHz and the logic consumes only 22uW/MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.321-327
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• 2006

This paper presents low power and high frequency design of instructions using ad-hoc techniques at transistor level for full custom and semi-custom ASIC(Application Specific Integrated Circuit) designs. The proposed design has been verified at high level using Verilog-HDL and simulated using ModelSim for the logical correctness. It is then observed at the layout level using LASI using $0.25{\mu}m$ technology and analyzed for timing characteristic under Win-spice simulation environment. The result shows the significant reduction up to $35\%$ in the power consumption by any general purpose processor like RISC or CISC. A significant reduction in the propagation delay is also observed. increasing the frequency for the fetch and execute cycle for the CPU, thus increasing the overall frequency of operation.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.4
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• pp.403-410
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• 2016

Materials made of metals have their own manifest resonant frequencies. Using this property, the quality test of products from the factory can be performed. An impact is applied to the product and the frequencies of the sound and/or vibration are measured using high-end equipments. They use a general purpose computer or a DSP(: Digital Signal Processor)-based stand-alone system which is usually too large in-size to carry and expensive to build. In this paper, we introduce a system that is developed based on a MSP430 MCU(:Micro-Controller Unit) from TI(: Texas Instruments). The ultra-low power MSP430 MCUs make it possible to make a frequency analyzer in a very small size without the need of using a large-size battery. The proposed system can be used in situations where the frequency analyzer should be carried easily with an investigator and should be built at low cost sacrificing some accuracy. We implemented the system using a launchpad supplied by TI and could confirm that the proposed system could identify with a high-accuracy the frequencies of various artificial and natural sounds.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.536-537
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• 2008

최근 홈 네트워킹 기술과 연동된 가전제어 및 서비스에 대한니즈가 증대�� 있어 다양한 디지털 가전기기가 개발되고 있다. 특히 국내외적으로 많은 홈 네트워크 관련 제품들이 생산되고 있으며 이는 궁극적으로 이기종 네트워크 환경에서 유무선 통신의 구된 없이 다양한 기기를 네트워크에 접속할 수 있는 서비스를 제공한다. 기존 중 저속 전력선 모뎀의 경우 홈 네트워크에서 전력선으로 들어오는 신호를 수신하기 위해 전력소모가 가장 많은 Main Processor에서는 항상 Wake-On 상태를 유지하고 있다. 하지만 중 저속 전력선 모뎀의 송수신을 관장하는 Main Processor를 보게 되면 크게 통신 프로토콜을 관장하는 Main CPU와 실제 전력선 신호 송수신을 관장하는 PLC Core로 나뉠 수 있다. 홈네트워크상에 전력선으로 들어오는 신호를 수신하기 위해서는 PLC Core는 항상 Wake-On 상태를 유지해야 하지만 Main CPU의 경우는 전력소모를 최소화하기 위해 Idle 상태를 유지하더라도 Host Controller와의 Stand-by & Wake On 신호와 인터럽트 발생기능을 이용하게 되면 전력선 통신에 문제가 없이 대기모드를 지원하는 저전력 전력선 통신 모뎀 개발이 가능하다. 이에 본 연구에서는 저전력 대기모드를 지원하는 전력선 통신 모뎀 개발에 관한 연구를 하고자 한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.4
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• pp.888-894
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• 2015

This paper describes an efficient hardware design of Lightweight Encryption Algorithm (LEA) developed by National Security Research Institute(NSRI). The LEA crypto-processor supports for master key of 128-bit. To achieve small-area and low-power implementation, an efficient hardware sharing is employed, which shares hardware resources for encryption and decryption in round transformation block and key scheduler. The designed LEA crypto-processor was verified by FPGA implementation. The LEA core synthesized with Xilinx ISE has 1,498 slice elements, and the estimated throughput is 216.24 Mbps with 135.15 MHz.

• The KIPS Transactions:PartA
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• v.15A no.5
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• pp.269-274
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• 2008

Recently, lots of embedded processors which can run streaming multimedia with high resolution display are introduced. Among the applications running on these embedded processors, real-time audio streaming is one of the applications that suffer from the lack of energy and memory space. In this paper, we propose a novel data compression method on scratch-pad memory, which saves both useful space on the scratch-pad memory and energy. We have implemented the data compression scheme on the GDM1202 real-time audio streaming processor, and the performance results show that we obtained 13.3% energy saving while maintaining comparable application performance to that of the non-compression case.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.401-403
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• 2015

This paper describes an efficient hardware design of 128-bit block cipher algorithm LEA(lightweight encryption algorithm). In order to achieve area-efficient and low-power implementation, round block and key scheduler block are optimized to share hardware resources for encryption and decryption. The key scheduler register is modified to reduce clock cycles required for key scheduling, which results in improved encryption/decryption performance. FPGA synthesis results of the LEA processor show that it has 2,364 slices, and the estimated performance for the master key of 128/192/256-bit at 113 MHz clock frequency is about 181/162/109 Mbps, respectively.

• The Journal of the Acoustical Society of Korea
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• v.20 no.8
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• pp.19-23
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• 2001

DSP-based implementation is pervasive in wireless communication parts for systems and handsets according to developing high-speed and low-power programmable Digital Signal Processor (DSP). In this paper, we present a real-time implementation of multi-channel Adaptive Multi-rate (AMR) speech coder. The real-time implementation of an AMR algorithm is achieved using 32-bit fixed-point TMS320C6202 DSP chip that operates at 250 MHz. We performed cross compile, linear assembly optimization and TMS320C62xx assembly optimization for real-time implementation. Furthermore, speech data input/output function and communication function with external CPU is included in an AMR speech coder. The AMR Speech coder developed using DSP EVM board was evaluated in ETRI IMT-2000 Test-bed system.