• Proceedings of the KIEE Conference
• /
• 2006.04a
• /
• pp.156-158
• /
• 2006

A super-regenerative receiver is designed and tested at 433 MHz ISM band, The designed receiver has the data rate of up to 200 kbps and a power consumption of 10 mW. We carried out the system performance test for the TX power of 0.1 mW and 1 m distance. The result of the bit-error rate test shows one bit error among the 4000 bits.

• Proceedings of the IEEK Conference
• /
• 2003.11c
• /
• pp.135-139
• /
• 2003

Sensor networks consist of sensor nodes with small-size, low-cost, low-power, and multi-functions to sense, to process and to communicate. Minimizing power consumption of sensors is an important issue in sensor networks due to limited power in sensor networks. Clustering is an efficient way to reduce data flow in sensor networks and to maintain less routing information. In this paper, we propose a multi-hop clustering mechanism using global and local ID to reduce transmission power consumption and an efficient routing method for improved data fusion and transmission.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.60 no.1
• /
• pp.19-26
• /
• 2011

In this paper, we designed Interpolation FIR(Finite Impulse Response) filter and 1-bit SDM(Sigma- Delta Modulator) for small digital audio speaker, which has low power consumption and high output characteristics. In order to achieve high linearity and low distortion performance of the systems, we adopt Type I Chevychev FIR filter which has equiripple characteristics in the pass band and proposed high efficient FIR filter structure. SDM is the most efficient modulation technique among the noise shaping techniques. In this paper, we implemented SDM using CIFB(Cascade of Intergrators, Feed-Back) which is generally used in DAC of small digital audio speakers. The proposed SDM structure can achieve high SNR, high-efficiency characteristics and low power consumption in mobile devices. Also considering manufacture of SoC(System on Chip), we performed simulation with Matlab and Verilog HDL to obtain optimal number of operational bits and verified a good experimental results.

• IEIE Transactions on Smart Processing and Computing
• /
• v.2 no.4
• /
• pp.248-254
• /
• 2013

The size and power consumption of digital circuits including the dimming circuit part will increase for high-performance solid state lighting (SSL) systems in the future. This study examined the low-power consumption of adiabatic dynamic CMOS logic (ADCL) due to the principles of adiabatic charging. Furthermore, the designed low-power ADCL digital pulse width modulation (PWM) was optimized for SSL dimming systems. For this purpose, an ADCL digital 3-bit PWM was optimized in two steps. In the first step, the architecture of the ADCL digital 3-bit PWM was miniaturized. In the second step, the clock cut-off circuit was designed and added to the ADCL PWM. As a result, compared to the original configuration, 60 transistors and 15 capacitors of ADCL digital 3-bit PWM were reduced for miniaturization. Moreover, the clock cut-off circuit, which controls wake-up and sleep mode of ADCL D-FFs, was designed. The power consumption of an optimized ADCL digital PWM for all bit patterns decreased by 54 %.

• Journal of Internet of Things and Convergence
• /
• v.6 no.2
• /
• pp.11-18
• /
• 2020

Since the end devices of the Internet of Things (IoT) are battery operated products, careful consideration for ultra-low power (ULP) is required. The Micro Controller Unit (MCU) industry has developed very effective functions to save energy, but developers have difficulty in selecting the MCU because various operating modes are applied to reduce energy consumption by manufacturers. Therefore, this paper introduces ULPMark benchmark, a standardized benchmark method that can compare MCUs of various vendors and feature sets, and provides hardware functions for ultra-low-power operation of the two platforms that received the high evaluation scores from ULPMark. In addition, we investigated and analyzed how developers can utilize the functions for ultra low power consumption through driver APIs and detailed register control.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.2 s.332
• /
• pp.41-48
• /
• 2005

In this paper, we propose a new Low-Swing CVSL full adder for low power consumption. An $8\times8$ parallel multiplier is used for the comparison between the proposed Low-Swing CVSL full adder with conventional CVSL full adder. Comparing the previous works, this circuit is reduced the power consumption rate of $13.1\%$ and the power-delay-product of $14.3\%$. The validity and effectiveness of the proposes circuits are verified through the HSPICE under Hynix $0.35{\mu}m$ standard CMOS process.

• Proceedings of the KIEE Conference
• /
• 2006.10c
• /
• pp.606-608
• /
• 2006

This paper describes a 8bit 10MS/s low power pipelined analog-to-digital converter(ADC). To reduce power consumption in proposed ADC, a high gain op-amp that consumes large power in MDAC(multiplying DAC) of conventional pipelined ADC is replaced with simple comparator and current sources. Moreover, differential charge transfer amplifier technique with latch in the sub-ADC reduces the power consumption to less than half compared with the conventional sub-ADC which use high speed comparator. The proposed ADC shows the power consumption of 1.8mW at supply voltage of 1.8V. This proposed ADC is suitable to apply to the portable display device. The circuit was implemented with 0.18um CMOS technology and the core size of circuit is 2.5mm${\times}$1mm.

• Journal of information and communication convergence engineering
• /
• v.5 no.2
• /
• pp.131-135
• /
• 2007

In this paper, The proposed algorithm consists of three steps. In the first step, TD(Transition Density) calculation has to be performed. a CLB-based CPLD low-power technology mapping algorithm considered a Trade-off is proposed. To perform low-power technology mapping for CPLDs, a given Boolean network has to be represented in a DAG. Total power consumption is obtained by calculating the switching activity of each node in a DAG. In the second step, the feasible clusters are generated by considering the following conditions: the number of inputs and outputs, the number of OR terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low-power technology mapping based on the CLBs packs the feasible clusters. The proposed algorithm is examined using SIS benchmarks. When the number of OR terms is five, the experiment results show that power consumption is reduced by 30.73% compared with TEMPLA, and by 17.11 % compared with PLA mapping.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.703-706
• /
• 1998

This paper presents an efficient substrate-bias generator(SBG)for low-power, high-density DRAM's The proposed SBG can supply stable voltage with switching the supply voltage of driving circuit, and it can substitude the small capacitance for the large capacitance. The charge pumping circuit of the SBG suffere no VT loss and is to be applicable to low-voltage DRAM's. Also it can reduce the power consumption to make VBB because of it's high pumping efficiency. Using biasing voltage with positive temperature coefficient, VBB level detecting circuit can detect constant value of VBB against temperature variation. VBB level during VBB maintaining period varies 0.19% and the power dissipation during this period is 0.16mw. Charge pumping circuit can make VBB level up to -1.47V using VCC-1.5V, and do charge pumping operation one and half faster than the conventional ones. The temperature dependency of the VBB level detecting circuit is 0.34%. Therefore the proposed SBG is expected to supply a stable VBB with less power consumption when it is used in low power DRAM's.

• 제어로봇시스템학회:학술대회논문집
• /
• 2001.10a
• /
• pp.114.6-114
• /
• 2001

According to expansion of wireless communication system and mobile device, interest has been growing in personal navigation system integrated with wireless system. In portable consumer electronics, such as cellular phones, GPS and PDA, one of major design factors is the power consumption. Solutions of reducing the power dissipation are low voltage, low system clock power management and so on. This paper develops a GPS receiver based on the advanced power management algorithm that achieves very low average power consumption. Both RF and DSP chips are powered down and reactivated only when the position fixing is required. In order to run, the developed includes the RTC calibration function and the fast reacquisition function using XMC (eXtended Multiple Correlator) ...