• Title/Summary/Keyword: Low-power Consumption

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Method for Power control of Wired and Wireless linkage Sensor Network for Low-power Wireless network (저전력 무선 네트워크를 위한 유무선 연동 센서 네트워크의 전력 제어 방법)

  • Lee, Kyung-Sook;Kim, Hyun-Deok
    • Convergence Security Journal
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    • v.12 no.3
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    • pp.27-34
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    • 2012
  • In this paper, using a new low-power consumption method for ZigBee device, which consume low-power using an output power control algorithm through RSSI monitoring as interlocking wireless network using ZigBee which has advantages of a low-power consumption, a low-cost, a compatibility and a draft international standardization enacted by IEEE and ZigBee Alliance, with wired network using built coaxial cable to overcome the disadvantage of the existing wireless sensor network, is proposed. Effectiveness of the output power control algorithm through RSSI monitoring has been verified by experimentation for more optimized low-power consumption.

Effect of Pulp Properties on the Power Consumption in Low Consistency Refining

  • LIU, Huan;DONG, Jixian;QI, Kai;GUO, Xiya;YAN, Ying;QIAO, Lijie;DUAN, Chuanwu;ZHAO, Zhiming
    • Journal of the Korean Wood Science and Technology
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    • v.48 no.6
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    • pp.869-877
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    • 2020
  • The power consumption in the low consistency (LC) refining is an important indicator for the optimal control of the process and it is composed of the net power and the no-load power. The refining efficiency and process characterization of LC refining are directly affected by power consumption. In this paper, the effect of pulp consistency and average fiber length on the power consumption and refining efficiency were studied through the LC refining trials conducted by an experimental disc refiner. It is found that the curve of power-gap clearance can be divided into constant power section, power reduction section, and power increase section. And the no-load power and the adjustable domain of loading applied by the refining plates will increase as the increase of pulp consistency, while the increase of net power is larger than that of no-load power which makes the increasing of refining efficiency. Meanwhile, the adjustable domain of loading applied by the refining plates can be slightly improved by increasing the average fiber length, but its effect on the no-load power in the LC refining process can be neglected. The study of power consumption in LC refining is of positive significance for the proper selection of pulp properties in LC refining, in-depth exploration of refining mechanism, and energy consumption reduction in refining.

Design of Low Power Motion Estimation for MPEG-4 (MPEG-4를 위한 저전력 Motion Estimation 설계)

  • 최홍규;이문기
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.851-854
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    • 2003
  • The low power motion estimation for MPEG-4 is a soft-core for hardwired motion estimation block in MPEG-4. This motion estimation is modified by 10 difference mode. So, this motion estimation decrease a power consumption compare conventional step search. This modified 4SS Low power Motion Estimation has been tested and verified to be valid for implementation of FPGA. The average PSNR between the original image and the motion-compensated image is 28.25dB. And Power consumption is 26mW.

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New Drowsy Cashing Method by Using Way-Line Prediction Unit for Low Power Cache (저전력 캐쉬를 위한 웨이-라인 예측 유닛을 이용한 새로운 드로시 캐싱 기법)

  • Lee, Jung-Hoon
    • Journal of The Institute of Information and Telecommunication Facilities Engineering
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    • v.10 no.2
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    • pp.74-79
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    • 2011
  • The goal of this research is to reduce dynamic and static power consumption for a low power cache system. The proposed cache can achieve a low power consumption by using a drowsy and a way prediction mechanism. For reducing the static power, the drowsy technique is used at 4-way set associative cache. And for reducing the dynamic energy, one among four ways is selectively accessed on the basis of information in the Way-Line Prediction Unit (WLPU). This prediction mechanism does not introduce any additional delay though prediction misses are occurred. The WLPU can effectively reduce the performance overhead of the conventional drowsy caching by waking only a drowsy cache line and one way in advance. Our results show that the proposed cache can reduce the power consumption by about 40% compared with the 4-way drowsy cache.

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Low-Power-Consumption Repetitive Wake-up Scheme for IoT Systems (사물인터넷 시스템을 위한 저전력 반복 깨우기 기법)

  • Kang, Kai;Kim, Jinchun;Eun, Seongbae
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.25 no.11
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    • pp.1596-1602
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    • 2021
  • Battery-operated IoT devices in IoT systems require low power consumption. In general, IoT devices enter a sleep state synchronously to reduce power consumption. A problem arises when an IoT device has to handle asynchronous user requests, as the duty cycle must be reduced to enhance response time. In this paper, we propose a new low-power-consumption scheme, called Repetitive Wake-up scheme for IoT systems of asynchronous environments such as indoor lights control. The proposed scheme can reduce power consumption by sending wake-up signals from the smartphone repetitively and by retaining the IoT device in sleep state to the smallest possible duty cycle. In the various environments with IoT devices at home or office space, we showed that the proposed scheme can reduce power consumption by up to five times compared to the existing synchronous interlocking technique.

Design Strategy of Low-Power Node by Analyzing the Hardware Modules in Surveillance and Reconnaissance Sensor Networks (감시정찰 센서네트워크에서 하드웨어 모듈의 소모전력 분석을 통한 저전력 노드 설계 전략)

  • Kim, Yong-Hyun;Yeo, Myung-Ho;Chung, Kwangsue
    • Journal of the Korea Institute of Military Science and Technology
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    • v.15 no.6
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    • pp.761-769
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    • 2012
  • In this paper, we propose a low-power design strategy to minimize energy-consumption for surveillance and reconnaissance sensor networks. The sensor network consists of many different nodes with various operations such as target detection, packet relay, video monitoring, changing protocols, and etc. Each sensor node consists of sensing, computing, communication, and power components. These components are integrated on a single or multiple boards. Therefore, the power consumption of each component can be different on various operation types. First, we identified the list of components and measured power consumption for them from the first prototype nodes. Next, we focus on which components are the main sources of energy consumption. We propose many energy-efficient approaches to reduce energy consumption for each operation type.

A Low Power Algorithm using State Transition Ready Method (상태 전환 준비 방법을 이용한 저전력 알고리즘)

  • Youn, Choong-Mo
    • The Journal of the Korea institute of electronic communication sciences
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    • v.9 no.9
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    • pp.971-976
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    • 2014
  • In this paper, we proposed a low power algorithm using state transition ready method. The proposed algorithm defined a sleep state, a idle state and a run state for the task. A state transition occurring at the time due to the delay time created in order to reduce the power consumption state in the middle of each inserted into the ready state. The ready state considering a power consumption and a delay time in state transition. A scheduling step of performing the steps in excess of the increasing problems have the delay time is long. The power consumption increased for the operation step increase. A state transition from a sleep state with the longest delay time in operating state occurs when the state is switched by the time delay caused by the increase in operating time reduces the overall power consumption reduced. Experiments [6] were compared with the results of the power consumption. The experimental results [6] is reduced power consumption than the efficiency of the algorithm has been demonstrated.

A Study on Battery Driven Low Power Algorithm in Mobile Device (이동기기에서 배터리를 고려한 저전력 알고리즘 연구)

  • Kim, Jae-Jin
    • Journal of the Korea Society of Computer and Information
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    • v.16 no.2
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    • pp.193-199
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    • 2011
  • In this paper, we proposed battery driven low power algorithm in mobile device. Algorithm the mobile devices in power of the battery for the task to perform power consumption to reduce the frequency alters. Power of the battery perform to a task power consumption of is less than the task perform to frequency the lower. Frequency control the task, depending on in the entire system devices used among the highest frequency with devices first target perform to. Frequency in the decrease the second largest frequency with of the device the frequency in changes the power consumption to calculate. The calculated consumption power the battery of level is greater than level the frequency by adjusting power consumption, lower power of the battery the task perform when you can to the frequency to adjust. Experiment the frequency by adjusting power consumption a method to reduce using [6] and in the same environment power of the battery consider the task to perform frequency were controlled. The results in [6] perform does not battery power on task operates that the result was.

A Phase Compensation for a Low Power Operational Trans-Conductance Amplifier

  • Yamauchi, Tsutomu;Takahashi, Kazukiyo;Yokoyama, Michio;Shouno, Kazuhiro;Mizunuma, Mitsuru
    • Proceedings of the IEEK Conference
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    • 2002.07a
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    • pp.337-340
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    • 2002
  • This paper describes a phase compensation technique for the low power consumption OTA. Power consumption of the low power OTA is lower than that of the conventional Wang's OTA. However. this circuit has an oscillation problem. The phase margin is -24deg. By using the phase compensation capacitor, the phase margin becomes 52deg. As a result, the low power consumption OTA circuit becomes to have an enough phase margin and to operate stably.

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The study on low power design of 8-bit Micro-processor with Clock-Gating (Clock-gating 을 고려한 저전력 8-bit 마이크로프로세서 설계에 관한 연구)

  • Jeon, Jong-Sik
    • The Journal of the Korea institute of electronic communication sciences
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    • v.2 no.3
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    • pp.163-167
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    • 2007
  • In this paper, to design 8 bit RISC Microprocessor, a method of Clock Gating to reduce electric power consumption is proposed. In order to examine the priority, the comparison results of between a 8 bit Microprocessor which is not considered Low Power consumption and which is considered Low Power consumption using a methods of Clock Gating are represented. Within the a few periods, the results of comparing with a Microprocessor not considered the utilization of Clock Gating shows that the reduction of dynamic dissipation is minimized up to 21.56%.

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