1 |
D. Garrett, M. Stan, and A. Dean, "Challenges in clock gating for a low-power ASIC methodology," In Proc. ISLPED, San Diego, CA, Aug. 1999, pp. 176-181.
|
2 |
P. Babighian and E. Macii, "A Scalable Algorithm for RTL Insertion of Gated Clocks Based on ODCs Computation," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 1, Jan. 2005, pp. 29-42.
DOI
ScienceOn
|
3 |
Y. Bae, "Diagnosis of power supply by analysis of chaotic nonlinear dynamics," J. of the Korea Institute of Electronic Communication Sciences, vol. 8, no. 1, 2013, pp. 13-19.
과학기술학회마을
DOI
ScienceOn
|
4 |
H. Wei, L. Yang, and L. Hanzo, "Interference-free broadband single-and multicarrier DSCDMA," IEEE Commun Mag., vol. 43, no. 2, 2005, pp. 68-73.
|
5 |
S. Kim, K. Kang, M. Kweon, and Y. Rhee, "Implementation of Zigbee/PLC Gateway System for U-Health Care," J. of the Korea Institute of Electronic Communication Sciences, vol. 5, no. 3, 2010, pp. 332-338.
과학기술학회마을
|
6 |
J. Kim and H. Kim, "Implement of a Bookshelf Management System using Powerline Communication and RF-ID," J. of the Korea Institute of Electronic Communication Sciences, vol. 5 no. 3, 2010, pp. 288-293.
과학기술학회마을
|
7 |
H. Bae, "Diagnosis of power supply by analysis of chaotic nonlinear dynamics," J. of the Korea Institute of Electronic Communication Sciences, vol. 5, no. 1, 1997, pp. 23-28.
|