• 대한전자공학회논문지SD
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• 제43권10호
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• pp.134-139
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• 2006

본 논문은 버스의 소비 전력을 비용 함수로 정의하여 버스의 소비 전력을 줄이는 버스 기반 평면계획을 제안한다. 기존 버스 기반 평면계획의 비용함수는 버스의 면적만을 줄이고 버스의 소비전력은 고려하지 않았다. 그러나 버스의 분할 설계 방식을 가정한 경우 버스의 소비 전력이 면적에 반드시 비례하지는 않기 때문에 기정의 비용함수로는 버스의 소비 전력을 반영할 수가 없다. 본 논문에서는 버스 분할 설계 기법이 적용된 경우를 가정하고 버스에 연결된 블록간의 통신량과 실제 거리를 고려하여 버스의 소비 전력을 비용함수에 추가하였다. 실험 결과 새로운 비용함수를 사용한 버스 기반 평면계획에서는 버스의 소비 전력에 관련된 값이 평균 11.43%만큼 감소하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.436-442
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• 2014

A new bus-invert coding circuit, called Two-bit Bus-Invert Coding (TBIC) is presented. TBIC partitions a bus into a set of two-bit sub-buses, and applies the bus-invert (BI) algorithm to each sub-bus. Unlike ordinary BI circuits using invert-lines, TBIC does not use an invert-line, so that it sends coding information through a bus-line. To transmit 3-bit information with 2 bus-lines, TBIC allows one bus-line to have a mid-level state, called M-state. TBIC increases the performance of BI algorithm, by suppressing the generation of overhead transitions. TBIC reduces bus transitions by about 45.7%, which is 83% greater than the maximum achievable performance of ordinary BI with invert-lines.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권2호
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• pp.75-79
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• 2009

A system-on-a-chip communication architecture has a significant impact on the performance and power consumption of modern multi-processors system-on-chips (MPSoCs). However, customization of such architecture for a specific application requires the exploration of a large design space. Thus, system designers need tools to rapidly explore and evaluate communication architectures. In this paper we present the method for application-specific low-power bus architecture synthesis at system-level. Our paper has two contributions. First, we build a bus power model of AMBA AXI bus communication architecture. Second, we incorporate this power model into a low-power architecture exploration algorithm that enables system designers to rapidly explore the target bus architecture. The proposed exploration algorithm reduces power consumption by 20.1% compared to a maximally connected reduced matrix, and the area is also reduced by 20.2% compared to the maximally connected reduced matrix.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1081-1084
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• 1998

In this paper, we propose the bus coding technique for low power consumption. For CMOS circuit most power is dissipated as dynamic power for charging and discharging node capacitances.Though the I/O and bus are likely to have the very large capacitances associated with them and dissipate much of the power dissipated by an IC, they have little beenthe special target for power reduction. The conventional Bus-Invert coding method can't decrease the peak power dissipation by 50% because the additional invert signal line can invoke a transition at the time when Bus-Invert coding isn't used to code original bus data. The proposed technique always constraints the Hamming distance between data transferred sequentially to be below the half of the bus width, and thus decrease the I/O peak power dissipation and the I/O average power dissipation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.745-753
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• 2016

This paper presents a fully synthesizable low power interconnect bus for millimeter-scale wireless sensor nodes. A segmented ring bus topology minimizes the required chip real estate with low input/output pad count for ultra-small form factors. By avoiding the conventional open drain-based solution, the bus can be fully synthesizable. Low power is achieved by obviating a need for local oscillators in member nodes. Also, aggressive power gating allows low-power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with a power management unit that has nW standby mode. A 3-module system including the bus is fabricated in a 180 nm process. The entire system consumes 8 nW in standby mode, and the bus achieves 17.5 pJ/bit/chip.

• ETRI Journal
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• 제32권4호
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• pp.540-547
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• 2010

One of the critical issues in on-chip serial communications is increased power consumption. In general, serial communications tend to dissipate more energy than parallel communications due to bit multiplexing. This paper proposes a low-power bus serialization method. This encodes bus signals prior to serialization so that they are converted into signals that do not greatly increase in transition frequency when serialized. It significantly reduces the frequency by making the best use of word-to-word and bit-by-bit correlations presented in original parallel signals. The method is applied to the revision of an MPEG-4 processor, and the simulation results show that the proposed method surpasses the existing one. In addition, it is cost-effective when implemented as a hardware circuit since its algorithm is very simple.

• 한국정보과학회논문지:시스템및이론
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• 제29권12호
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• pp.680-686
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• 2002

딥 서브 마이크론 (DSM: deep-submicron) 설계에서는 버스에서 선들 간의 커플링 효과는 크로스톡 지연, 노이즈, 전력 소모와 같은 심각한 문제를 야기 시킨다. 버스 인코딩에 대한 대부분의 이전 연구들은 버스에서의 전력 소모를 최소화하거나 크로스톡 지연을 최소화하는데 초점을 맞추고 있지만 모두를 고려한 방법은 보이지 않는다. 이 논문에서, 우리는 버스에서의 전력 소모 최소화와 크로스톡 지연 방지를 동시에 고려한 새로운 버스 인코딩 알고리즘을 제안하였다. 우리는 이 문제를 공식화하여, 자체 천이와 상호 천이의 가중 합 문제를 풂으로써 해결하였다. 여러 벤치마크 설계를 이용한 실험으로부터 제안한 인코딩 방법을 이용할 경우, 크로스톡 지연을 완전히 제거할 뿐 아니라 이전의 방법들을 사용한 것 보다 최소 15% 이상 적은 전력을 소모하였음을 보았다.

• Journal of Power Electronics
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• 제16권4호
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• pp.1256-1267
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• 2016

Distributed stray inductance exerts a significant influence on the turn-off voltages of power switching devices. Therefore, the design of low stray inductance bus bars has become an important part of the design of high-power converters. In this study, we first analyze the operational principle and switching transient of a T-type converter. Then, we obtain the commutation circuit, categorize the stray inductance of the circuit, and study the influence of the different types of stray inductance on the turn-off voltages of switching devices. According to the current distribution of the commutation circuit, as well as the conditions for realizing laminated bus bars, we laminate the bus bar of the converter by integrating the practical structure of a capacitor bank and a power module. As a result, the stray inductance of the bus bar is reduced, and the stray inductance in the commutation circuit of the converter is reduced to more than half. Finally, a 10 kVA experimental prototype of a T-type converter is built to verify the effectiveness of the designed laminated bus bar in restraining the turn-off voltage spike of the switching devices in the converter.

• 한국항행학회논문지
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• 제21권6호
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• pp.620-625
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• 2017

최근 사람이 다수 붐비는 지역에 스마트 폰이나, 태블릿 등을 바로 충전할 수 있는 태양광 모듈이 설치되어 서비스를 제공하고 있다. 하지만 버스 출입과 관련된 정보의 연동이 불가능 하여 충전 중인 스마트 폰이나, 태블릿 등을 두고 버스에 승차하여 분실하는 문제가 발생한다. 본 논문에서는 이와 같은 문제를 해결하기 위해 LPWA 기술과 BLE의 Advertising mode를 이용하여 버스가 접근 할 때 스마트폰으로 알려주는 시스템을 제안한다. 실험결과 NLOS에서 낮은 위치에 존재하는 수신 단말과 버스에 장착된 단말간 통신거리가 최대 640 m인 것을 확인하였으며 이를 통해 약 2~3분 전에 버스의 도착 알람을 받을 수 있는 것을 확인하였으며, Ble의 서비스 거리가 최대 87 m로 버스 정류장 인근에 있어도 서비스를 제공받을 수 있는 것을 확인하였다.

• Journal of Power Electronics
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• 제9권3호
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• pp.447-455
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• 2009

The power supply systems, which require low-voltage / high-current output has been changing from the conventional centralized power system to a distributed power system. The distributed power system consists of a bus converter and POL. The most important factor is the system stability in bus architecture design. The overlap between the output impedance of a bus converter input impedance of POL causes system instability and has been an actual problem. By increasing the bus capacitor, the system stability can be easily improved. However, due to limited space on the system board, the increasing of bus capacitors is impractical. An urgent solution of this issue is strongly desired. This paper presents the output impedance design for on-board distributed power system by means of three control schemes of a bus converter. The output impedance peak of the bus converter and the input impedance of the POL are analyzed and then conformed experimentally for stability criterion. Furthermore, the design process of each control schemes for system stability is proposed.