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http://dx.doi.org/10.4218/etrij.10.0109.0447

On-Chip Bus Serialization Method for Low-Power Communications  

Lee, Jae-Sung (Software Research Laboratory, ETRI)
Publication Information
ETRI Journal / v.32, no.4, 2010 , pp. 540-547 More about this Journal
Abstract
One of the critical issues in on-chip serial communications is increased power consumption. In general, serial communications tend to dissipate more energy than parallel communications due to bit multiplexing. This paper proposes a low-power bus serialization method. This encodes bus signals prior to serialization so that they are converted into signals that do not greatly increase in transition frequency when serialized. It significantly reduces the frequency by making the best use of word-to-word and bit-by-bit correlations presented in original parallel signals. The method is applied to the revision of an MPEG-4 processor, and the simulation results show that the proposed method surpasses the existing one. In addition, it is cost-effective when implemented as a hardware circuit since its algorithm is very simple.
Keywords
Low-power design; multimedia; on-chip bus; system-on-chip; bus serialization;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
Times Cited By Web Of Science : 8  (Related Records In Web of Science)
Times Cited By SCOPUS : 11
연도 인용수 순위
1 S.M. Kim et al., "Hardware-Software Implementation of MPEG-4 Video Codec," ETRI J., vol. 25, no 6, Dec. 2003, pp. 489-502.   과학기술학회마을   DOI   ScienceOn
2 SuperH, "SuperHyway On-Chip Interconnect Solution," 2003.
3 Palmchip, "CoreFrame Architecture," 2002.
4 STMicroelectronics, "STBus Interconnect," 2004.
5 OpenCores, "Wishbone bus," 2003.
6 ARM, "AMBA AXI Protocol Specification," 2003.
7 VSI Alliance, "Virtual Component Interface Standard," 2000.
8 OCP International Partnership, "Open Core Protocol Specification," 2001.
9 P.E. Landman and J.M. Rabaey, "Architectural Power Analysis: The Dual Bit Type Method," IEEE Trans. VLSI Syst., vol. 3, no. 2, June 1995, pp. 173-187.   DOI
10 M.R. Stan and W.P. Burleson, "Bus-Invert Coding for Low-Power I/O," IEEE Trans. VLSI Syst., vol. 3, no. 1, Mar. 1995, pp. 49-58.   DOI
11 P. Panda and N. Dutt, "Reducing Address Bus Transitions for Low Power Memory Mapping," Proc. Int. Symp. Design Automation Test Eur., 1996, pp. 63-67.
12 L. Benini et al., "Asymptotic Zero-Transition Activity Encoding for Address Buses in Low-Power Microprocessor-Based Systems," Proc. 7th Great Lakes Symp. VLSI, 1997, pp. 77-82.
13 S. Ramprasad, N. Shanbhag, and I. Hajj, "A Coding Framework for Low-Power Address and Data Busses," IEEE Trans. VLSI Syst., vol. 7, no. 2, June 1999, pp. 212-221.   DOI
14 Y. Aghaghiri, F. Fallah, and M. Pedram, "Irredundant Address Bus Encoding for Low Power," Proc. Int. Symp. Low-Power Electron. Design, 2001, pp. 182-187.
15 L. Macchiarulo, E. Macii, and M. Poncino, "Low-Energy for Deep-Submicron Address Buses," Proc. Int. Symp. Low-Power Electron. Design, 2001, pp. 176-181
16 R.R. Rao et al., "Bus Encoding for Total Power Reduction Using a Leakage-Aware Buffer Configuration," IEEE Trans. VLSI Syst., vol. 13, no. 12, Dec. 2005, pp. 1376-1383.   DOI
17 K.M. Lee, S.J. Lee, and H.J. Yoo, "Low-Power Network-On-Chip for High-Performance SoC Design," IEEE Trans. VLSI Syst., vol. 14, Feb. 2006, pp. 148-160.   DOI
18 K. Lee et al., "A 51 mW 1.6 GHz Network for Low-Power Heterogeneous SoC Platform," ISSCC Dig. Tech. Papers, 2004, pp. 152-153.
19 S.J. Lee et al., "An 800 MHz Star-Connected On-Chip Network for Application to Systems on a Chip," ISSCC Dig. Tech. Papers, 2003, pp. 468-469.
20 S. Kimura et al., "An On-Chip High Speed Serial Communication Method Based on Independent Ring Oscillators," ISSCC Dig. Tech. Papers, 2003, pp. 390-391.
21 ARM, "AMBA Specification, Rev. 2.0," 1999.
22 IBM, "CoreConnect Bus Architecture," 1999.