• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.53-57
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• 2017

This paper proposes a 401MHz-406MHz low noise amplifier for MedRadio applications. The proposed low noise amplifier adopts a common gate amplifier topology using current reuse gm-boosting technique. The proposed low noise amplifier shows better performance of voltage gain and noise figure than the conventional gm-boosted common gate amplifier in the same power consumption. The proposed current-reuse gm-boosted low noise amplifier achieves a voltage gain of 22 dB, a noise figure of 2.95 dB, and IIP3 of -17 dBm while consuming $170{\mu}W$ from a 0.5 V supply voltage in $0.13{\mu}m$ CMOS process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.6
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• pp.853-856
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• 2021

In this paper, a low noise amplifier having high gain and low noise by using input and inter stage matching circuits has been designed. A current-reused two-stage common-source topology is adopted, which can obtain high gain and low power consumption. Deterioration of noise characteristics according to the source inductive degeneration matching is compensated by adopting additional matching circuits. Moreover trade-offs among noise, gain, linearity, impedance matching, and power dissipation have been considered. In this design, 0.18-mm CMOS process is employed for the simulation. The simulated results show that the designed low noise amplifier can provide high power gain and low noise characteristics.

• Journal of the Korean Institute of Telematics and Electronics
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• v.9 no.4
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• pp.17-24
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• 1972

A simply constructed and inexpensive amplifier that exhibits unusually low noise is studied. The high-performance differential amplifier combines high input impedence, adjustable gain, low in put noise and low output impedance. The amplifier is particularly useful in applications which call for large amplificaions of very low level signals.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.897-904
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• 2011

In this paper, a novel circuit topology of a low-noise amplifier tunable at 1.8GHz band for PCS and 2.4GHz band for WLAN using a CMOS active inductor is proposed. This circuit topology to reduce higher noise figure of the low noise amplifier with the CMOS active load is analyzed. Furthermore, the noise canceling technique is adopted to reduce more the noise figure. The noise figure of the proposed circuit topology is analyzed and simulated in $0.18{\mu}m$ CMOS process technology. Thus, the simulation results exhibit that the noise performance enhancement of the tunable low noise amplifier is about 3.4dB, which is mainly due to the proposed new circuit topology.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.309-312
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• 2002

In this paper, we discuss the design of high gain low noise amplifier by using the 0.2sum CMOS technology. A cascode inverter is adopted to implement the low noise amplifier. The proposed cascode inverter LNA is one stage amplifier with a voltage reference and without choke inductors. The designed 2.4GHz LNA achieves a power gain of 25dB, a noise figure of 2.2dB, and power consumption of 255㎽ at 2.5V power supply.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.191-194
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• 1999

The balanced amplifier is a practical amplifier to, implement a broadband amplifier that has flat gain and good input and output VSWR. Three-stage amplifier design procedure usually divided into three partition satisfying the following requirements : low noise figure, high gain and high power output. FHX35LG HEMT device is used in the design can be obtained low noise figure at the first-stage, MGA82563 MMIC device is used in the design can be maintained high gain at the second-stage, and AHI MMIC device is used in the design can be required high power output at the third-stage. The results of three-stage balanced amplifier show that power gain is about 40㏈, noise figure is less than 1.2㏈ at operating frequency.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.12
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• pp.1159-1164
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• 2016

This study describes the design and implementation of SHF band Low Noise Amplifier of Digital Satellite Communication. We have applied to HEMT part to minimize Noise Figure of system. and minimized the potential for the occurrence of such erroneous operation of equipment through the simulations of the space environment. We designed a reliable Low Noise Amplifier through simulation for a TID according to the vibration generated during the launch and space radiation environment, and compared pre-simulation of main performance results to test results about main performances of Low Noise Amplifier after production.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.381-384
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• 2000

In this paper, we designed and fabricated a low noise amplifier which can be used in W-CDMA. For improving input VSWR and stability an emitter inductance series feedback was used, and for acquiring higer linearity at low current DC bais by-passing method was used. Fabricated low noise amplifier had 15.33 ㏈ power gain, 2.17 ㏈ NF, -9.53 ㏈ $S_{11}$ and -35.91 ㏈ $S_{22}$ at 2.16 GHz, and +5.34 ㏈m II $P_{ 3}$ at 10 MHz channel spacing.g.g.g.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.318-330
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• 2013

This paper presents a high-linearity low-noise small-size programmable gain amplifier (PGA) based on a new low-noise low-distortion differential amplifier and a proposed reconfiguration technique. The proposed differential amplifier combines an inverter-based differential pair with an adaptive biasing circuit to reduce noise and distortion. The reconfiguration technique saves the chip size by half by utilizing the same differential pair for the input transconductance and load-stage, interchangeably. Fabricated in $0.18-{\mu}m$ CMOS, the proposed PGA shows a dB-linear control range of 21dB in 16 steps from -11 dB to 10 dB with a gain error of less than ${\pm}0.33$ dB, an IIP3 of 7.4~14.5 dBm, a P1dB of -7~1.2 dBm, a noise figure of 13dB, and a 3-dB bandwidth of 270MHz at the maximum gain, respectively. The PGA occupies a chip area of $0.04mm^2$ and consumes only 1.3 mA from the 1.8 V supply.

• Journal of Sensor Science and Technology
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• v.31 no.2
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• pp.120-124
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• 2022

With advancements in underwater stealth technology for naval vessels, new sensor configurations for detecting targets have been attracting increased attention. Latest underwater mines adopt multiple sensor configurations that include electric field sensors to detect targets and to help acquire accurate ignition time. An underwater electric field sensor consists of a pair of electrodes, signal processing unit, and preamplifier. For detecting underwater electric fields, the preamplifier requires low-noise amplification at ultra-low frequency bands. In this paper, the specific requirements for low-noise preamplifiers are discussed along with the experimental results of various setups of matched transistors and chopper stabilized operational amplifiers. The results showed that noise characteristics at ultra-low frequency bands were affected significantly by the voltage noise density of the chopper amplifier and the number of matched transistors used for differential amplification. The fabricated preamplifier was operated within normal design parameters, which was verified by testing its gain, phase, and linearity.