• Journal of the Semiconductor & Display Technology
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• v.11 no.2
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• pp.71-74
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• 2012

Uniformity of the wafer temperature is one of the important factors in etching process. Plasma, chucking force, backside helium pressure and the surface temperature of ESC(electrostatic chuck) affect the wafer temperature. ESC consists of several layers of structure. Each layer has own thermal resistance and the Si-adhesive layer has highest thermal resistance among them. In this work, the temperature distribution of ESC was analyzed by 3-D FEM with various defects and the thickness deviation of the Si-adhesive layer. The result with Si-adhesive layer with the low center thickness deviation shows modified temperature distribution of ESC surface.

• ETRI Journal
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• v.25 no.2
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• pp.65-72
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• 2003

To achieve cost and size reductions, we developed a low cost manufacturing technology for RF substrates and a high performance passive process technology for RF integrated passive devices (IPDs). The fabricated substrate is a conventional 6" Si wafer with a 25${\mu}m$ thick $SiO_2$ surface. This substrate showed a very good insertion loss of 0.03 dB/mm at 4 GHz, including the conductive metal loss, with a 50 ${\Omega}$ coplanar transmission line (W=50${\mu}m$, G=20${\mu}m$). Using benzo cyclo butene (BCB) interlayers and a 10 ${\mu}m$ Cu plating process, we made high Q rectangular and circular spiral inductors on Si that had record maximum quality factors of more than 100. The fabricated inductor library showed a maximum quality factor range of 30-120, depending on geometrical parameters and inductance values of 0.35-35 nH. We also fabricated small RF IPDs on a thick oxide Si substrate for use in handheld phone applications, such as antenna switch modules or front end modules, and high-speed wireless LAN applications. The chip sizes of the wafer-level-packaged RF IPDs and wire-bondable RF IPDs were 1.0-1.5$mm^2$ and 0.8-1.0$mm^2$, respectively. They showed very good insertion loss and RF performances. These substrate and passive process technologies will be widely utilized in hand-held RF modules and systems requiring low cost solutions and strict volumetric efficiencies.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.647-650
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• 2006

Low temperature polycrystalline silicon (LTPS) technology using a high power laser have been widely applied to thin film transistors (TFTs) for liquid crystal, organic light emitting diode (OLED) display, driver circuit for system on glass (SOG) and static random access memory (SRAM). Recently, the semiconductor industry is continuing its quest to create even more powerful CPU and memory chips. This requires increasing of individual device speed through the continual reduction of the minimum size of device features and increasing of device density on the chip. Moreover, the flat panel display industry also need to be brighter, with richer more vivid color, wider viewing angle, have faster video capability and be more durable at lower cost. Kornic Systems Co., Ltd. developed the $KORONA^{TM}$ LTP/GLTP series - an innovative production tool for fabricating flat panel displays and semiconductor devices - to meet these growing market demands and advance the volume production capabilities of flat panel displays and semiconductor industry. The $KORONA^{TM}\;LTP/GLTP$ series using DPSS laser and XeCl excimer laser is designed for the new generation of the wafer & FPD glass annealing processing equipment combining advanced low temperature poly-silicon (LTPS) crystallization technology and object-oriented software architecture with a semistandard graphical user interface (GUI). These leading edge systems show the superior annealing ability to the conventional other method. The $KORONA^{TM}\;LTP/GLTP$ series provides technical and economical benefits of advanced annealing solution to semiconductor and FPD production performance with an exceptional level of productivity. High throughput, low cost of ownership and optimized system efficiency brings the highest yield and lowest cost per wafer/glass on the annealing market.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.11
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• pp.2085-2092
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• 2016

One of the most important properties of the IC substrate is that it should be uniform over large areas. Among the various physical approaches of wafer defect characterization, special attention is to be payed to the infrared techniques of inspection. In particular, a high spatial resolution, near infrared absorption method has been adopted to directly observe defects in semi-insulating GaAs. This technique, which relies on the mapping of infrared transmission, is both rapid and non-destructive. This method demonstrates in a direct way that the infrared images of GaAs crystals arise from defect absorption process. A new interpretation is presented for the observed reversal of contrast in the infrared absorption of nonuniformly distributed deep centers, related to EL2, in semi-insulating GaAs. The low temperature photoquenching experiment has demonstrated in a direct way that the contrast inverse images of GaAs wafers arise from both absorption and scattering mechanisms rather than charge re-distribution or local variation of bandgap.

• Journal of the Korean Solar Energy Society
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• v.39 no.3
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• pp.9-17
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• 2019

Laser cutting cell of solar cells can achieve high voltage and efficiency through more array than conventional 6 inch cell compared to same area. In this study, we fabricated c-Si cutting cell with various lasers and laser conditions such as power, speed, and number of times. In the case of picosecond laser, excellent surface characteristics were obtained due to small surface defects and low thermal damage at the output of 20W and the speed of 100 mm/s. However, it is not possible to fabricate a cutting cell having good characteristics due to nonuniform cutting inside the wafer when the processing for forming a cutting cell is not sufficiently performed. For nanosecond lasers, the best wafer characteristics were obtained for fabrication of excellent cutting cells at a frequency of 500 kHz and a laser speed of 100 mm/s. However, the nanosecond laser has not been processed sufficiently in the condition of a number of times. As a result, it was confirmed that the wafer thickness was cut by $63{\mu}m$ of the cell thickness of $170{\mu}m$ in the condition of five times of laser process. It was found that more than 30% of the wafer thickness had to be processed to fabricate the cutting cell. After cutting the 6-inch cell having the voltage of 0.65 V, we obtained the voltage of about 0.63 V.

• Bulletin of the Korean Chemical Society
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• v.31 no.5
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• pp.1295-1300
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• 2010

The $CO_2-CH_4$ reaction catalyzed by Ni/silicon wafers was kinetically studied by using a photoacoustic technique. The catalytic reaction was performed at various partial pressures of $CO_2$ and $CH_4$ (50 Torr total pressure of $CO_2/CH_4/N_2$) in the temperature range of 500 - $650^{\circ}C$ in a static reactor system. The photoacoustic signal that varied with the $CO_2$ concentration during the catalytic reaction was recorded as a function of time. Under the reaction conditions, the $CO_2$ photoacoustic measurements showed the as-prepared Ni thin film sample to be inactive for the reaction, while the $CO_2/CH_4$ reactions carried out in the presence of the sample pre-treated in $H_2$ at $600^{\circ}C$ were associated with significant time-dependent changes in the $CO_2$ photoacoustic signal. The rate of $CO_2$ disappearance was measured from the $CO_2$ photoacoustic signal data in the early reaction period of 50 - 150 sec to obtain precise kinetic data. The apparent activation energy for $CO_2$ consumption was determined to be 6.9 kcal/mol from the $CO_2$ disappearance rates. The partial reaction orders, determined from the $CO_2$ disappearance rates measured at various $PCO{_2}'S$ and $PCH{_4}'S$ at $600^{\circ}C$, were determined to be 0.33 for $CH_4$ and 0.63 for $CO_2$, respectively. Kinetic data obtained in these measurements were compared with previous works and were discussed to construct a catalytic reaction mechanism for the $CO_2-CH_4$ reaction over Ni/silicon wafer at low pressures.

• Journal of the Korean Solar Energy Society
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• v.32 no.spc3
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• pp.194-198
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• 2012

Crystalline silicon solar cell remains the major player in the photovoltaic marketplace with 80% of the market, despite the development of various thin film technologies. Silicon's excellent efficiency, stability, material abundance and low toxicity have helped to maintain its position of dominance. However, the cost of silicon materials remains a major barrier to reducing the cost of silicon photovoltaics. Using the crystalline silicon wafer with thinner thickness is the promising way for cost and material reduction in the solar cell production. However, the thinner the silicon wafer is, the worse bow phenomenon is induced. The bow phenomenon is observed when two or more layers of materials with different temperature expansion coefficiencies are in contact, in this case silicon and aluminum. In this paper, the solar cells were fabricated with different thicknesses of Al layer in order to reduce the bow phenomenon. With less amount of paste applications, we observed that the bow could be reduced by up to 40% of the largest value with 120 micron thickness of the wafer even though the conversion efficiency decrease by 0.5% occurred. Since the bowed wafers lead to unacceptable yield losses during the module construction, the reduction of bow is indispensable on thin crystalline silicon solar cell. In this work, we have studied on the counterbalance between the bow and conversion efficiency and also suggest the formation of enough back surface field (BSF) with thinner Al layer application.

• 한국태양에너지학회:학술대회논문집
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• 2012.03a
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• pp.108-112
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• 2012

Crystalline silicon solar cell remains the major player in the photovoltaic marketplace with 90 % of the market, despite the development of a variety of thin film technologies. Silicon's excellent efficiency, stability, material abundance and low toxicity have helped to maintain its position of dominance. However, the cost of silicon photovoltaic remains a major barrier to reducing the cost of silicon photovoltaics. Using the crystalline silicon wafer with thinner thickness is the promising way for cost and material reduction in the solar cell production. However, the thinner thickness of silicon wafer is, the worse bow phenomenon is induced. The bow phenomenon is observed when two or more layers of materials of different temperature expansion coefficiencies are in contact, in this case silicon and aluminum. In this paper, the solar cells were fabricated with different thicknesses of Al layer in order to reduce the bow phenomenon. With lower paste applications, we observed that the bow could be reduced by up to 40% of the largest value with 130 micron thickness of the wafer even though the conversion efficiency decrease of 0.5 % occurred. Since the bowed wafers lead to unacceptable yield losses during the module construction, the reduction of bow is indispensable on thin crystalline silicon solar cell. In this work, we have studied on the counterbalance between the bow and conversion efficiency and also suggest the formation of enough back surface field (BSF) with thinner Al paste application.

• Journal of Sensor Science and Technology
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• v.22 no.1
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• pp.89-94
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• 2013

In this paper, we developed a beam of MEMS probe card using a BeCu sheet. Silicon wafer thickness of $400{\mu}m$ was fabricated by using deep reactive ion etching (RIE) process. After forming through silicon via (TSV), the silicon wafer was bonded with BeCu sheet by soldering process. We made BeCu beam stress-free owing to removing internal stress by using joule heating. BeCu beam was fused by using joule heating caused by high current. The fabricated BeCu beam measured length of 1.75 mm and width of 0.44 mm, and thickness of $15{\mu}m$. We measured fusing current as a function of the cutting planes. Maximum current was 5.98 A at cutting plane of $150{\mu}m^2$. The proposed low-cost and simple fabrication process is applicable for producing MEMS probe beam.

• Transactions on Electrical and Electronic Materials
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• v.7 no.4
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• pp.163-166
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• 2006

The dishing and the erosion were evaluated on the tungsten CMP process with conventional and new developed slurry. The tungsten thin film was polished by orbital polishing equipment. Commercial pattern wafer was used for the evaluation. Both slurries were pre tested on the oxide region on the wafer surface and the removal rate was not different very much. At the pattern density examination, the erosion performance was increased at all processing condition due to the reduction of thickness loss in new slurry. However, the dishing thickness was not remarkably changed at high pattern density despite of the improvement at low pattern density. At the large pad area, the reduction of dishing thickness was clearly found at new tungsten slurry.