• 한국전자파학회논문지
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• 제17권6호
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• pp.574-586
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• 2006

최근 세계 무선 통신 환경은 선진국가별로 다양한 통신 기술에 대한 기준 마련 및 표준화가 진행되고 있다. 이에 따른 통신 환경 변화에 대처하기 위하여 국내에서도 여러 분야에 걸쳐 다양하게 기술 기준 및 표준화에 대한 연구가 진행되고 있다. 본 연구에서는 미약 무선국의 전계 강도(기술 기준)에 대한 현재 각국의 동향과 그 기준치를 연구 분석하고, 파악함과 동시에, 또한, 전자파 적합 등록에서 제시하고 있는 각국의 전계 강도 기준치와 연계하여 이에 적합한 국내의 비허가 무선 기기(미약 무선 기기)의 실질적인 도입 가능한 전계 강도의 기준치를 제시함을 목적으로 한다. 여기에서 제시한 전계 강도 허용치를 바탕으로, 미약 무선 기기의 보급과 발전에 기여할 것으로 예상되며 국내 통신 시장은 물론 국제 통신 시장에서 경쟁력을 갖출 수 있을 것으로 예상된다.

• 신재생에너지
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• 제16권3호
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• pp.1-12
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• 2020

Shingled technology is the latest cell interconnection technology developed in the photovoltaic (PV) industry due to its reduced resistance loss, low-cost, and innovative electrically conductive adhesive (ECA). There are several advantages associated with shingled technology to develop cell to module (CTM) such as the module area enlargement, low processing temperature, and interconnection; these advantages further improves the energy yield capacity. This review paper provides valuable insight into CTM loss when cells are interconnected by shingled technology to form modules. The fill factor (FF) had improved, further reducing electrical power loss compared to the conventional module interconnection technology. The commercial PV module technology was mainly focused on different performance parameters; the module maximum power point (Pmpp), and module efficiency. The module was then subjected to anti-reflection (AR) coating and encapsulant material to absorb infrared (IR) and ultraviolet (UV) light, which can increase the overall efficiency of the shingled module by up to 24.4%. Module fabrication by shingled interconnection technology uses EGaIn paste; this enables further increases in output power under standard test conditions. Previous research has demonstrated that a total module output power of approximately 400 Wp may be achieved using shingled technology and CTM loss may be reduced to 0.03%, alongside the low cost of fabrication.

• 정보학연구
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• 제5권4호
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• pp.1-8
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• 2002

본 연구는 저압 전력선에서의 데이터 통신에 적합한 변조 방식으로 주목받고 있는 다중 반송 변조의 일종인 OFDM(Orthogonal Frequency Division Multiplexing)의 변조를 실험하고, 이들 데이터를 전달 할 매체인 전력선을 채널 모델링 하였다. 전력선은 각종 전자기기에 의해 분기 연결되어 지연 전파의 경우와 임펄스성 잡음원이 존재하는 것으로 알려져 있다. 반송 주파수와 전력선의 길이에 의해 주파수 선택적 페이딩이 발생함을 알 수 있다.

• Journal of Power Electronics
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• 제14권6호
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• pp.1293-1302
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• 2014

A flyback inverter using voltage sensorless maximum power point tracking (MPPT) for photovoltaic (PV) AC modules is presented. PV AC modules for a power rating from 150 W to 300 W are generally required for their small size and low price because of the installation on the back side of PV modules. In the conventional MPPT technique for PV AC modules, sensors for detecting PV voltage and PV current are required to calculate the PV output power. However, system size and cost increase when the voltage sensor and current sensor are used because of the addition of the auxiliary circuit for the sensors. The proposed method uses only the current sensor to track the MPP point. Therefore, the proposed control method overcomes drawbacks of the conventional control method. Theoretical analysis, simulation, and experiment are performed to verify the proposed control method.

• International journal of advanced smart convergence
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• 제11권1호
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• pp.28-35
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• 2022

This paper presents a performance evaluation of real-time Linux for industrial real-time platforms. On industrial platforms, multicore processors are popular due to their work distribution efficiency and cost-effectiveness. Multicore processors, however, are not designed for applications with real-time constraints, and their performance capabilities depend on their core configurations. In order to assess the feasibility of a multicore processor for real-time applications, we conduct a performance evaluation of a general processor and a low-power processor to provide an experimental environment of real-time Linux on both Xenomai and RT-preempt considering the multicore configuration. The real-time performance is evaluated through scheduling latency and in an environment with loads on the CPU, memory, and network to consider an actual situation. The results show a difference between a low-power and a general-purpose processor, but from developer's point of view, it shows that the low-power processor is a proper solution to accommodate low power situations.

• Journal of Electrical Engineering and Technology
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• 제4권4호
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• pp.559-565
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• 2009

Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. The high switching activity of combinational circuits is an unnecessary operation in scan shift mode. In this paper, we present a novel architecture to reduce test power dissipation in combinational logic by blocking signal transitions at the logic inputs during scan shifting. We propose a unique architecture that uses dmuxed scan flip-flop (DSF) and transmission gate as an alternative to muxed scan flip-flop. The proposed method does not have problems with auto test pattern generation (ATPG) techniques such as test application time and computational complexity. Moreover, our elegant method improves performance degradation and large overhead in terms of area with blocking logic techniques. Experimental results on ITC99 benchmarks show that the proposed architecture can achieve an average improvement of 30.31% in switching activity compared to conventional scan methods. Additionally, the results of simulation with DSF indicate that the powerdelay product (PDP) and area overhead are improved by 28.9% and 15.6%, respectively, compared to existing blocking logic method.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 심포지엄 논문집 정보 및 제어부문
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• pp.156-158
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• 2006

A super-regenerative receiver is designed and tested at 433 MHz ISM band, The designed receiver has the data rate of up to 200 kbps and a power consumption of 10 mW. We carried out the system performance test for the TX power of 0.1 mW and 1 m distance. The result of the bit-error rate test shows one bit error among the 4000 bits.

• Journal of information and communication convergence engineering
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• 제5권2호
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• pp.131-135
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• 2007

In this paper, The proposed algorithm consists of three steps. In the first step, TD(Transition Density) calculation has to be performed. a CLB-based CPLD low-power technology mapping algorithm considered a Trade-off is proposed. To perform low-power technology mapping for CPLDs, a given Boolean network has to be represented in a DAG. Total power consumption is obtained by calculating the switching activity of each node in a DAG. In the second step, the feasible clusters are generated by considering the following conditions: the number of inputs and outputs, the number of OR terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low-power technology mapping based on the CLBs packs the feasible clusters. The proposed algorithm is examined using SIS benchmarks. When the number of OR terms is five, the experiment results show that power consumption is reduced by 30.73% compared with TEMPLA, and by 17.11 % compared with PLA mapping.

• Journal of information and communication convergence engineering
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• 제9권6호
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• pp.729-732
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• 2011

Power consumption during testing System-On-Chip (SOC) is becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.114.6-114
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• 2001

According to expansion of wireless communication system and mobile device, interest has been growing in personal navigation system integrated with wireless system. In portable consumer electronics, such as cellular phones, GPS and PDA, one of major design factors is the power consumption. Solutions of reducing the power dissipation are low voltage, low system clock power management and so on. This paper develops a GPS receiver based on the advanced power management algorithm that achieves very low average power consumption. Both RF and DSP chips are powered down and reactivated only when the position fixing is required. In order to run, the developed includes the RTC calibration function and the fast reacquisition function using XMC (eXtended Multiple Correlator) ...