• 제목/요약/키워드: Low-Power Circuit Design

검색결과 778건 처리시간 0.038초

저전력 고속 NCL 비동기 게이트 설계 (Design of Low Power and High Speed NCL Gates)

  • 김경기
    • 전자공학회논문지
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    • 제52권2호
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    • pp.112-118
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    • 2015
  • 기존의 동기방식의 회로는 나노미터 영역에서의 공정, 전압, 온도 변이 (PVT variation), 그리고 노화의 영향으로 시스템의 전체 성능을 유지할 수 없을 뿐만 아니라 올바른 동작을 보장할 수도 없다. 따라서 본 논문에서는 여러 가지 변이에 영향을 받지 않는 비동기회로 설계 방식 중에서 타이밍 분석이 요구되지 않고, 설계가 간단한 DI(delay insentive) 방식의 NCL (Null Convention Logic) 설계 방식을 이용하여 디지털 시스템을 설계하고자 한다. 기존의 NCL 게이트들의 회로 구조들은 느린 스피드, 높은 영역 오버헤드, 높은 와이어(wire) 복잡도와 같은 약점을 가지고 있기 때문에 본 논문에서는 빠른 스피드, 낮은 영역 오버헤드, 낮은 와이더 복잡도를 위해서 트랜지스터 레벨에서 설계된 새로운 저전력 고속 NCL 게이트 라이브러리를 제안하고자 한다. 제안된 NCL 게이트들은 동부 0.11um 공정으로 구현된 비동기 방식의 곱셈기의 지연, 소모 전력에 의해서 기존의 NCL 게이트 들과 비교되었다.

DRAM의 저전력, 고속화에 따른 VDC 설계에 관한 연구 (A Study on the Design of the Voltage Down Converter for Low Power, High Speed DRAM)

  • 주종두;곽승욱
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1998년도 추계종합학술대회 논문집
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    • pp.707-710
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    • 1998
  • This paper presents a new voltage down converter(VDC) for low power, high speed DRAM. This VDC Consists of RVG(Reference Voltage Generator) and Driver Circuit. And it is independent of temperature variation, and Supply Voltage. Using weak inversion region, this RVG dissipates low power. Internal Voltage Source of this VDC is stable in spite of high speed operation of memory array. This circuit is designed with a $0.65\mu\textrm{m}$ nwell CMOS technology. In HSPICE simulation results, Temperature dependency of this RVG is $20\muV/^{\circ}C,$ supply voltage dependency is $\pm0.17%,$ $VCC=3.3V\pm0.3V,$ and current dissipation is $5.22\muA.$ Internal voltage source bouncing of this VDC is smaller than conventional VDC.

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저궤도 위성 자세제어용 센서 RLG 전원 공급기 설계 (The RLG's Power Supply Design for Attitude Control in the Satellite)

  • 김의찬;이흥호
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2008년도 제39회 하계학술대회
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    • pp.1488-1490
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    • 2008
  • The gyroscope is the sensor for detecting the rotation in inertial reference frame and constitute the navigation system together an accelerometer. As the inertial reference equipment for attitude determination and control in the satellite, the mechanical gyroscope has been used but it bring the disturbance for mass unbalance so the disturbance give a bad influence to the observation satellite mission because the mechanical gyroscope has the rotation parts. During the launch, The mechanical gyroscope is weak in vibration, shock and has the defect of narrow operating temperature range so it need the special design in integration. Recently the low orbit observation satellite for seeking the high pointing accuracy of image camera payload accept the FOG(Fiber Optic Gyro) or RLG(Ring Laser Gyro) for the attitude determination and control. The Ring Laser Gyro makes use of the Sanac effect within a resonant ring cavity of a He-Ne laser and has more accuracy than the other gyros. It need the 1000V DC to create the He-Ne plasma in discharge tube. In this paper, the design process of the High Voltage Power Supply for RLG(Ring Laser Gyroscope) is described. The specification for High Voltage Power Supply(HVPS) is proposed. Also, The analysis of flyback converter topology is explained. The Design for the HVPS is composed of the inverter circuit, feedback control circuit, high frequency switching transformer design and voltage doubler circuit.

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Low Dropout Voltage Regulator Using 130 nm CMOS Technology

  • Marufuzzaman, Mohammad;Reaz, Mamun Bin Ibne;Rahman, Labonnah Farzana;Mustafa, Norhaida Binti;Farayez, Araf
    • Transactions on Electrical and Electronic Materials
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    • 제18권5호
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    • pp.257-260
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    • 2017
  • In this paper, we present the design of a 4.5 V low dropout (LDO) voltage regulator implemented in the 130 nm CMOS process. The design uses a two-stage cascaded operational transconductance amplifier (OTA) as an error amplifier, with a body bias technique for reducing dropout voltages. PMOS is used as a pass transistor to ensure stable output voltages. The results show that the proposed LDO regulator has a dropout voltage of 32.06 mV when implemented in the130 nm CMOS process. The power dissipation is only 1.3593 mW and the proposed circuit operates under an input voltage of 5V with an active area of $703{\mu}m^2$, ensuring that the proposed circuit is suitable for low-power applications.

저압계통 보호 엔지니어링을 위한 시각화 소프트웨어 개발 (A Development of Visualization Software for Protective Engineering in Low-Voltage Power Systems)

  • 윤상윤;이남호;이욱화;이진;김재철
    • 대한전기학회논문지:전력기술부문A
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    • 제55권7호
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    • pp.297-305
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    • 2006
  • This paper summarizes a development of visualization software for protective engineering in low-voltage power systems. The study is concentrated on the following aspects. First, a software engineering method is applied for designing the object-oriented program. The design and implementation of a Graphic User Interface(GUI) and its integration to a power system framework are developed using object-oriented programming(OOP) in Visual C++. Second, we develop the short circuit analysis module that oriented a low-voltage power system. It is possible to calculate a peak, symmetrical RMS, DC component and asymmetrical fault currents for each time. And it is the first software that can calculate the fault current for single branch of three-phase system. The calculation accuracy is compared with commercial software, and the libraries of low-voltage components are served for convenience use. Third, protective engineering functions are equipped. It is possible to automatically select the circuit breaker which based on the user input characteristics and the fault current calculation and examine the protective coordination. Through the case study, we verified that the developed software can be effectively used to examine the protective engineering in low-voltage power systems.

Bulk-Driven 기법을 이용한 저전압 Analog Multiplier (The Low Voltage Analog Multiplier Using The Bulk-driven MOSFET Techniques)

  • 문태환;권오준;곽계달
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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    • pp.301-304
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    • 2001
  • The analog multiplier is very useful building block in many circuits such as filter, frequency-shifter, and modulators. In recent year, The main design issue of circuit designer is low-voltage/low-power system design, because of all systems are recommended very integrated system and portable system In this paper, the proposed the four-quadrant analog multiplier is using the bulk-driven techniques. The bulk-driven technique is very useful technique in low-voltage system, compare with gate-driven technique. therefore the proposed analog multiplier is operated in 1V supply voltage. And the proposed analog multiplier is low power dissipation compare with the others. therefor the proposed analog multiplier is convenient in low-voltage/low-power in system.

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다양한 매칭 회로들을 활용한 저잡음 증폭기 설계 연구 (Design of Low Noise Amplifier Utilizing Input and Inter Stage Matching Circuits)

  • Jo, Sung-Hun
    • 한국정보통신학회논문지
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    • 제25권6호
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    • pp.853-856
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    • 2021
  • In this paper, a low noise amplifier having high gain and low noise by using input and inter stage matching circuits has been designed. A current-reused two-stage common-source topology is adopted, which can obtain high gain and low power consumption. Deterioration of noise characteristics according to the source inductive degeneration matching is compensated by adopting additional matching circuits. Moreover trade-offs among noise, gain, linearity, impedance matching, and power dissipation have been considered. In this design, 0.18-mm CMOS process is employed for the simulation. The simulated results show that the designed low noise amplifier can provide high power gain and low noise characteristics.

IMT-2000용 저전력 디지털 정합 필터의 설계 (Design of Low-Power Digital Matched Filter for IMT-2000 system)

  • 박기현;하진석;이광엽;차재상
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2004년도 하계종합학술대회 논문집(1)
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    • pp.31-34
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    • 2004
  • In wireless communication systems, low-power metrics is becoming a burdensome problem in the portable terminal design, because of portability constraints. This paper presents design architecture of a low-power partial correlation Digital Matched Filter for the IMT-2000 communication systems. The proposed approach focuses on efficient circuit size, power dissipation, maintaining the operating throughput. The proposed architecture was verified by using Xilinx FPGA.

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선박 평형수 처리용 대전류 인버터 방식의 정류기 설계 (Design of High-Current Inverter-type Rectifier for Electrolytic Disinfection of Ship Ballast Water)

  • 조원우;김진영;김인동;노의철;고강우;배상범
    • 전력전자학회논문지
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    • 제16권5호
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    • pp.430-439
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    • 2011
  • 세계화와 더불어 수출 입 물동량이 크게 늘어남에 따라 세계를 왕래하는 선박의 평형수(Ballast water) 속에 존재하는 해양 유기체에 의한 생태계의 파괴가 큰 문제가 되고 있다. 이와 같은 문제를 해결하기 위해 국제규약은 선박의 평형수를 배출할 때는 반드시 미생물을 제거한 다음 바다로 배출할 것을 요구하고 있다. 이는 위한 염소발생용 전기분해 수 처리 시스템을 위해 우수한 성능을 가지는 저전압 대전류 방식의 정류기의 필요성이 커지고 있다. 본 논문에서는 선박의 평형수 처리를 위한 해수 전기분해용 정류기에 적합한 저전압 대전류 정류기 방식을 제안하고, 정류기 전력회로 설계와 제어기 설계에 필요한 실제적인 설계 가이드라인을 제시하고자 한다.

넓은 부하범위에서 고효율 특성을 갖는 역율개선회로의 PWM 제어기 (PWM Controller of Power Factor Correction Circuit to Improve Efficiency for Wide Load Range)

  • 손민수;김홍중;박귀철;최재호
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2016년도 전력전자학술대회 논문집
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    • pp.75-76
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    • 2016
  • This paper proposes a power factor correction circuit with a high efficiency over a wide load range characteristics for a communication power supply. And the characteristic verification is applied to produce a design of prototype. Power factor correction circuit can reduce conduction losses by applying Bridgeless Boost Converter for efficiency. Over a wide load range to maintain the efficient, the control method of a PWM controller is divided by two sections according to the load area. In the low-load region, it was reduced switching losses by applying the critical conduction mode control method. On the other hand, in the heavy-load area, the hysteresis current control method is used to maintain the high efficiency over a wide load range by limiting the peak noise of the inductor.

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