• Journal of the Semiconductor & Display Technology
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• v.19 no.4
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• pp.88-93
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• 2020

Based on the capture-emission energy (CEE) maps of CMOS devices, a physics-informed machine learning model for the bias temperature instability (BTI)-induced threshold voltage shifts and low frequency noise is presented. In order to incorporate physics theories into the machine learning model, the integration of artificial neural network (IANN) is employed for the computation of the threshold voltage shifts and low frequency noise. The model combines the computational efficiency of IANN with the optimal estimation of Gaussian mixture model (GMM) with soft clustering. It enables full lifetime prediction of BTI under various stress and recovery conditions and provides accurate prediction of the dynamic behavior of the original measured data.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.12
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• pp.939-943
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• 2011

In this paper, reliability of the two sandwiched MIM capacitors of $Al_2O_3-HfO_2-Al_2O_3$ (AHA) and $SiO_2-HfO_2-SiO_2$ (SHS) with hafnium-based dielectrics was analyzed using two kinds of voltage stress; DC and AC voltage stresses. Two MIM capacitors have high capacitance density (8.1 fF/${\mu}m^2$ and 5.2 fF/${\mu}m^2$) over the entire frequency range and low leakage current density of ~1 nA/$cm^2$ at room temperature and 1 V. The charge trapping in the dielectric shows that the relative variation of capacitance (${\Delta}C/C_0$) increases and the variation of voltage linearity (${\alpha}$/${\alpha}_0$) gradually decreases with stress-time under two types of voltage stress. It is also shown that DC voltage stress induced greater variation of capacitance density and voltage linearity than AC voltage stress.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05c
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• pp.132-137
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• 2002

The mold transformers have been widely used in underground substations in large building and have some advantages in comparison to oil-transformer, that is low fire risk, excellent environmental compatibility, compact size and high reliability. In addition, the application of mold transformer for outdoor is possible due to development of epoxy resin. The mold transformer generally has cooling duct between low voltage coil and high voltage coil. A mold transformer made by one body molding method has been developed for small size and low loss. The life of transformer is significantly dependent on the thermal behavior in windings. To analyse winding temperature rise, many transformer designer have calculated temperature distribution and hot spot point by finite element method(FEM). Recently, numerical analyses of transformer are studied for optimum design, that is electric field analysis, magnetic field, potential vibration, thermal distribution and thermal stress. In this paper, the temperature distribution of 50 kVA pole mold transformer for power distribution are investigated by FEM program and the temperature rise test of designed mold transformer carried out and test result is analyzed compare to simulation data. In this result, the designed mold transformer is satisfied to limit value of temperature and the other property is good such as voltage ratio, winding resistance, no-load loss, load loss, impedance voltage and percent regulation.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1735-1742
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• 2016

This paper proposes an interleaved five-level boost converter based on a switched-capacitor network. The operating principle of the converter under the CCM mode is analyzed. A high voltage gain, low component stress, small input current ripple, and self-balancing function for the capacitor voltages in the switched-capacitor networks are achieved. In addition, a three-loop control strategy including an outer voltage loop, an inner current loop and a voltage-balance loop has been researched to achieve good performances and voltage-balance effect. An experimental study has been done to verify the correctness and feasibility of the proposed converter and control strategy.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.50 no.12
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• pp.601-608
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• 2001

The ever increasing density of adjustable speed drives(ASD) device with non-linear operating characteristics has been to put tremendous harmonic stress on end user's electrical application. All ASD controllers which employ solid state power devices cause harmonic currents in the source side line. This paper describes harmonic problems for use of ASD. In order to investigate the effect of harmonics caused by using of nonlinear load at the low voltage system, we fixed up simple load model and measured the voltage and current waveforms. Measurement results show that additional operation of linear load at the parallel bus with nonlinear load such as ASD is helpful to the reduction of harmonic influence.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.399-401
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• 2005

A new high performance energy-recovery circuit (ERC) for a plasma display panel (PDP) is proposed. Two different ERCs are employed on both sides of the PDP, and slow falling and fast rising times are applied. It features a zero voltage switching (ZVS), low electromagnetic interference (EMI), low current stress, high efficiency, no severe voltage notch, reduced sustaining voltage, and high energy-recovery capability.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.408-410
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• 2005

Multilevel converters have emerged like a new strategy for energy conversion from medium power to high power. The main characteristic of the topologies classified as multilevel, is the use of commutation devices connected in series, allowing the distribution of the voltage and reducing stress in the commutation switches. Stacked Multicell Converter (SMC), is classified as single-phase voltage source inverter(VSI). Due to the fact, the SMC generates a signal of alternating current of several levels of voltage of direct current. The following work will demonstrate the flexibility of the above mentioned topology using a low cost control circuit architecture.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.51 no.1
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• pp.10-17
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• 2002

Due to the development of information communication field, the interest of the SMPS(Switched Mode Power Supply) is increased. The size and weight of SMPS are decided by inductor, capacitor and transformer. Thus, the low loss converter which is operated in high speed switching is required. The resonant FB DC-DC converter is able to operate in high speed switching and apply to high power field because the switching loss is low. In this thesis, it is proposed to control strategy for constant output power of resonant FB DC-DC converter in variable input voltage. The proposed control system is a digital I-PD type control and apply to phase-shift resonant type controller. The output voltage tracks reference without steady state error in variable input voltage. The validity of proposed control strategy is verified from results of simulation and experiment.

• Journal of Electrical Engineering and Technology
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• v.9 no.5
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• pp.1592-1601
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• 2014

In this study, a novel single phase soft switched power factor correction (PFC) converter is developed with active snubber cell. The active snubber cell provides boost switch both to turn on with zero voltage transition (ZVT) and to turn off with zero current transition (ZCT). As the switching losses in the proposed converter are too low, L and C size can be reduced by increasing the operating frequency. Also, all the semiconductor devices operate with soft switching. There is no additional voltage stress in the boost switch and diode. The proposed converter has a simple structure, low cost and ease of control as well. It has a simple control loop to achieve near unity power factor with the aid of the UC3854. In this study, detailed steady state analysis of the proposed converter is presented and this theoretical analysis is verified by a prototype of 100 kHz and 500 W converter. The measured power factor and efficiency are 0.99 and 97.9% at full load.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.12
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• pp.792-796
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• 2014

In this paper, we investigated the hot carrier reliability of two kinds of device with low threshold voltage (LVT) and regular threshold voltage (RVT) in 65 nm CMOS technology. Contrary to the previous report that devices beyond $0.18{\mu}m$ CMOS technology is dominated by channel hot carrier(CHC) stress rather than drain avalanche hot carrier(DAHC) stress, both of LVT and RVT devices showed that their degradation is dominated by DAHC stress. It is also shown that in case of LVT devices, contribution of interface trap generation to the device degradation is greater under DAHC stress than CHC stress, while there is little difference for RVT devices.