• 전력전자학회논문지
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• 제5권2호
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• pp.154-162
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• 2000

본 논문에서는 3상 강압형 다이오드 정류기에서 출력전압의 저주파 리플 전압을 감소시키기 위한 새로운 제어기법을 제안한다. 제안한 펄스 주파수 변조 기법은 강압형 다이오드 정류기의 출력전압과 넓은 부하 범위에 대한 주 스위치의 영전류 스위칭을 보장하기 위해 적용된다. 본 논문에서 적용된 펄스 주파수 변조 기법은 일반적으로 입력전류의 낮은 고조파의 단위 역률의 장점을 지니고 있다. 또한 출력전압에서 보여진 저주파 리플전압을 감소시키기 위해 효과적으로 사용되어진다. 제안된 제어기법을 자세하게 설명하며 그 타당성을 검증하기 위해 시뮬레인션 및 실험을 통하여 검증한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.523-524
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• 2008

Proposed battery charger is a economic candidate because that is simple and small size. The circuit has linearly operational power stage. That use small size buffer with small driving current and large power MOS gate capacitance. The simulation result show that charging current is stable and has low ripple.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.357-360
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• 1999

A 20 MHz CMOS continuous low-pass filter using simulated floating inductor consisted of two fully-differential transconductors and a capacitor is presented. The theory of operation is described and simulation results show close agreement between predicted behaviour and experimential performance. Simulation results show that the filter has ripple bandwidth of 22 MHz, pass-band ripple of 0.36 ㏈. and cutoff frequency of 26 MHz at supplay voltage of $\pm$3 V. The power dissipation is 19.2 ㎽.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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• pp.708-712
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• 2001

A new phase-shifted parallel-input/series-output (PI SO) dual inductor-fed push-pull converter for high-power step­up applications is proposed. This converter is operated at a constant duty cycle and employs an auxiliary circuit to control the output voltage with a phase-shift between the two modules. It features a voltage conversion characteristic which is linear to changes in the control input, and high step-up ratio with a greatly reduced switch turn-off stress resulting in a significant increase in the converter efficiency. It also shows a low ripple content and low root-mean-square (RMS) current in the output capacitor. The operational principle is analyzed and a comparative analysis with the conventional pulse-width-modulated (PWM) PISO dual inductor-fed push-pull converter is presented. A 50kHz, 800W, 350Vdc prototype with an input of 20-32Vdc has also been constructed to validate the proposed converter. The proposed converter compares favorably with the conventional counterpart and is considered well suited to high-power step-up applications.

• Journal of Power Electronics
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• 제15권6호
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• pp.1429-1437
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• 2015

A new parallel hybrid soft switching converter with low circulating current losses during the freewheeling state and a low output current ripple is presented in this paper. Two circuit modules are connected in parallel using the interleaved pulse-width modulation scheme to provide more power to the output load and to reduce the output current ripple. Each circuit module includes a three-level converter and a half-bridge converter sharing the same lagging-leg switches. A resonant capacitor is adopted on the primary side of the three-level converter to reduce the circulating current to zero in the freewheeling state. Thus, the high circulating current loss in conventional three-level converters is alleviated. A half-bridge converter is adopted to extend the ZVS range. Therefore, the lagging-leg switches can be turned on under zero voltage switching from light load to full load conditions. The secondary windings of the two converters are connected in series so that the rectified voltage is positive instead of zero during the freewheeling interval. Hence, the output inductance of the three-level converter can be reduced. The circuit configuration, operation principles and circuit characteristics are presented in detail. Experiments based on a 1920W prototype are provided to verify the effectiveness of the proposed converter.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2003년도 춘계전력전자학술대회 논문집(1)
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• pp.481-484
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• 2003

A strategy for a torque ripple reduction drive of single-phase SRM with high power factor is proposed. The drive for switched reluctance motor (SRM) is presented to achieve sinusoidal, near unity power factor input current with low torque ripple. The proposed SRM drive has no additional active switch. And a single-stage approach, which combines a DC link capacitor used as dc source and a drive used for driving the motor into one power stage, has a simple structure and low cost. The characteristics and validity of the proposed circuit is discussed in depth through the experimental results.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2004년도 전력전자학술대회 논문집(2)
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• pp.959-962
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• 2004

A strategy for a torque ripple reduction drive of single-phase SRM with high power factor is proposed. The drive for switched reluctance motor (SRM) is presented to achieve sinusoidal, near unity power factor input current with low torque ripple. The proposed SRM drive has no additional active switch. And a single-stage approach, which combines a DC link capacitor used as do source and a drive used for driving the motor into one power stage, has a simple structure and low cost. The characteristics and validity of the proposed circuit is discussed in depth through the experimental results.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2002년도 전력전자학술대회 논문집
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• pp.343-346
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• 2002

In recent, complex SVPWM (Space Vector PWM) algorithm can be easily implemented by high performance microprocessor and DSP. Various SVPWM techniques are widely studied due to the advantages of low harmonic distortion and high use ratio of D.C. link voltage. Most of various studies for improving of VS-PWM inverter performance are concentrated about switching pattern and zero pulse pattern split algorithms. However, dc link voltage that is determined at rated load and speed conditions is not proper in the low speed and under rated load. In this paper, analysis of current ripple with digitally implemented SVPWM inverter is introduced according to link voltage. The optimal link voltage in the designed inverter system and load condition is provided in order to suppress output voltage error and current ripple. As remaining the effective voltage vector interval per sampling period sufficiently, additional voltage error and current ripple are suppressed. The proposed algorithm is verified through digital simulation and experimental results.

• Journal of Power Electronics
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• 제12권3호
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• pp.458-467
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• 2012

Single phase converters suffer from ripple power pulsating at twice the line frequency. The ripple power is usually absorbed by a bulky capacitor bank and/or a dedicative LC resonant link, resulting in a low power density and a high cost. An alternative solution is using a dc link active power filter (APF) to direct the pulsating power into another energy-storage component. The main dc link filter capacitor can then be reduced substantially. Based on a mainstream dc APF topology, this paper proposed a new control strategy incorporating both dual-loop control and repetitive control. The circuit parameter design is also re-examined from a control point of view. The proposed APF scheme has better control performance, and is more suited for high power applications since it works in CCM and with a low switching frequency.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 하계학술대회 논문집 B
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• pp.936-938
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• 2003

The single Phase induction motor is used to small size electronic appliance by production cost of a low-cost. But, it is low efficiency large torque ripple and impossible speed control. However we can change the speed if it similar to the three phase induction motor. And we studied about the two phase induction motor that torque ripple is smaller. So, in this paper the dynamic characteristics of the two phase induction motor are described and compared with the cage-type single phase induction motor to find the characteristics of the torque ripple and current, speed through the time-stepped finite element method.