• 반도체디스플레이기술학회지
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• 제2권3호
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• pp.25-30
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• 2003

In this study, the controller using TMS320LF2407 low voltage DSP for motor control is designed and realized. It has 40 MIPS calculating ability and its driving voltage is 3.3 V for low power. The peripheral elements, however usually use 5 V and they need voltage transfer interface. In this study, voltage transformation and reducing noise are studied and space vector PWM is adopted as a motor control scheme. According to these methods, the efforts for software programming and calculation processes are reduced. In addition, the hardware is also simplified by substituting the current control part with software programming. Through this study, the DSP based servo controller increases its ability for high performance multi-function on semiconductor transportation equipments..

• 전기학회논문지
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• 제57권4호
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• pp.543-550
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• 2008

This paper proposes an voltage and reactive power control methodology, which is motivated towards implementation in the korea power system. The main voltage control devices are capacitor banks, reactor banks and LTC transformers. Effects of control devices are evaluated by local subsystem's cost computations. This local subsystem is decided by 'Tier' and 'Electrical distance' in the whole system. The control objective at present is to keep the voltage profile within constraints with minimum switching cost. A robust control strategy is proposed to make the control feasible and optimal for a set of power-flow cases that may occur important event from system. This studies conducted for IEEE 39-bus low and high voltage contingency cases indicate that the proposed control methodology is much more effective than PSS/E simulation tool in deciding switching of capacitor and reactor banks.

• 한국전기전자재료학회논문지
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• 제22권1호
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• pp.7-11
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• 2009

In this study, p-channel silicon-oxide-nitride-oxide-silicon(SONOS) transistors are fabricated and characterized as an unit cell for NAND flash memory. The SONOS transistors are fabricated by $0.13{\mu}m$ low power standard logic process technology. The thicknesses of gate insulators are 2.0 nm for the tunnel oxide, 1.4 nm for the nitride layer, and 4.9 nm for the blocking oxide. The fabricated SONOS transistors show low programming voltage and fast erase speed. However, the retention and endurance of the devices show poor characteristics.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.15-16
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• 2005

Chalcogenide phase change memory has high performance to be next generation memory, because it is a nonvolatile memory processing high programming speed, low programming voltage, high sensing margin, low consumption and long cycle duration. We have developed a new material of PRAM with $Ge_1Se_1Te_2$. This material has been propose to solve the high energy consumption and high programming current. We have investigated the phase transition behaviors in function of various process factor including contact size, cell size, and annealing time. As a result, we have observed that programming voltage and writing current of $Ge_1Se_1Te_2$ are more improved than $Ge_2Sb_2Te_5$ material.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.1329-1330
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• 2007

Phase-change random access memory(PRAM) has many advantages compare with the existing memory. For example, fast programming speed, low programming voltage, high sensing margin, low power consume and long cyclability of read/write. Though it has many advantages, there are some points which must be improved. So, we invented and studied new constitution of $Ge_{1}Se_{1}Te_{2}$ chalcogenide material. Actually, the performance properties have been improved surprisingly. However, crystallization time was as long as ever for amorphization time. In this paper, we studied in order to make set operation time and reset operation voltage reduced. In the present work, by alloying Sb in $Ge_{1}Se_{1}Te_{2}$. we could confirm that improved its set operation time and reset operation voltage. As a result, the method of Sb-alloyed $Ge_{1}Se_{1}Te_{2}$ can be solution to decrease the set operation time and reset operation voltage.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.80-81
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• 2005

Chalcogenide phase change memory has high performance to be next generation memory, because it is a nonvolatile memory processing high programming speed, low programming voltage, high sensing margin, low consumption and long cycle duration. We have developed a sample of PRAM with thermal protected layer. We have investigated the phase transition behaviors in function of process factor including thermal protect layer. As a result, we have observed that set voltage and duration of protect layer are more improved than no protect layer.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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• pp.898-901
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• 2005

We propose a novel pixel structure using bootstrapped voltage programming for amorphoussilicon TFT backplane of AM-OLED (Active Matrix-Organic Light Emitting Diode) displays. The proposed structure is composed of two TFTs and one capacitor. It operates at low drive voltage ($0{\sim}5V$) which can reduce power consumption comparing with the conventional pixel circuit structure using same OLED material. Also, it can easily control dark level and use commercial mobile LCD ICs. In this paper, we describe the operating principle and the characteristics of the proposed pixel structure and verify the performance by SPICE simulation comparing with the conventional pixel structure.

• Journal of Electrical Engineering and Technology
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• 제12권5호
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• pp.1872-1882
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• 2017

Medium voltage drive systems driven by high-power multi-level inverters operating at low switching frequency can reduce the switching losses of the power device and increase the output power. Employing subsection synchronous current harmonic minimum pulse width modulation (CHMPWM) technique can maintain the total harmonic distortion of current at a very low level. It can also reduce the losses of the system, improve the system control performance and increase the efficiency of DC-link voltage accordingly. This paper proposes a subsection synchronous CHMPWM approach of active neutral point clamped five-level (ANPC-5L) inverter under low switching frequency operation. The subsection synchronous scheme is obtained by theoretical calculation based on the allowed maximum switching frequency. The genetic algorithm (GA) is adopted to get the high-precision initial values. So the expected switching angles can be achieved with the help of sequential quadratic programming (SQP) algorithm. The selection principle of multiple sets of the switching angles is also presented. Finally, the validity of the theoretical analysis and the superiority of the CHMPWM are verified through both the simulation results and experimental results.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 추계종합학술대회 B
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• pp.604-607
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• 2008

본 연구에서는 NAND 플래시메모리를 위한 기본 셀로서 p채널 SONOS (silicon-oxide-nitride-oxide-silicon) 트랜지스터를 제작하고 이것의 메모리특성을 조사하였다. SONOS 트랜지스터의 제작은 $0.13{\mu}m$ low power용 standard logic 공정기술을 사용하였다. 게이트 절연막의 두께는 터널 산화막 $20{\AA}$, 질화막 $14{\AA}$, 그리고 블로킹산화막의 두께는 $49{\AA}$이다. 제작된 SONOS 트랜지스터는 낮은 쓰기/지우기 전압, 빠른 지우기 속도, 그리고 비교적 우수한 기억유지특성과 endurance 특성을 나타내었다.

• E2M - 전기 전자와 첨단 소재
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• 제8권6호
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• pp.727-736
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• 1995

This paper examines the characteristics and physical properties of the scaled MONOS nonvolatile memory device for low programming voltage EEPROM. The capacitor-type MONOS memory devices with the nitride thicknesses ranging from 41.angs. to 600.angs. have been fabricated. As a result, the 5V-programmable MONOS device has been obtained with a 20ms programming time by scaling the nitride thickness to 57.angs. with a tunneling oxide thickness of 19.angs. and a blocking oxide thickness of 20.angs.. Measurement results of the quasi-static C-V curves indicate, after 10$\^$6/ write/erase cycles, that the devices are degraded due to the increase of the silicon-tunneling oxide interface traps. The 10-year retention is impossible for the device with a nitride less than 129.angs.. However, the MONOS memory device with 10-year retentivity has been obtained by increasing the blocking oxide thickness to 47.angs.. Also, the memory traps such as the nitride bulk trap and the blocking oxide-nitride interface trap have been investigated by measuring the maximum flatband voltage shift and analyzing through the best fitting method.