• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.125-128
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• 2001

In this paper, we propose a low power Scan-based Built-ln Self Test based on circuit partitioning and pattern suppression using modified test control unit. To partition a CUT(Circuit Under Testing), the MHPA(Multilevel Hypergraph Partition Algorithm) is used. As a result of circuit partition, we can reduce the total length of test pattern, so that power consumptions are decreased in test mode. Also, proposed Scan-based BIST architecture suppresses a redundant test pattern by inserting an additional decoder in BIST control unit. A decoder detects test pattern with high fault coverage, and applies it to partitioned circuits. Experimental result on the ISCAS benchmark circuits shows the efficiency of proposed low power BIST architecture.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.1
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• pp.199-202
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• 2009

Scan design is currently the most widely used structured Design For Testability approach. In scan design, all storage elements are replaced with scan cells, which are then configured as one or more shift registers(also called scan chains) during the shift operation. As a result, all inputs to the combinational logic, including those driven by scan cells, can be controlled and all outputs from the combinational logic, including those driving scan cells, can be observed. The scan inserted design, called scan design, is operated in three modes: normal mode, shift mode, and capture mode. Circuit operations with associated clock cycles conducted in these three modes are referred to as normal operation, shift operation, and capture operation, respectively. In spite of these, scan design methodology has defects. They are power dissipation problem and test time during test application. We propose a new methodology about scan shift clock operation and present low power scan design and short test time.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.640-648
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• 2014

Excessive power dissipation is one of the major issues in the testing of VLSI systems. Many techniques are proposed for scan test, but there are not so many for logic BIST because of its unmanageable randomness. This paper presents a novel low switching activity BIST scheme that reduces toggle frequency in the majority of scan chain inputs while allowing a small portion of scan chains to receive pseudorandom test data. Reducing toggle frequency in the scan chain inputs can reduce test power but may result in fault coverage loss. Allowing a small portion of scan chains to receive pseudorandom test data can make better uniform distribution of 0 and 1 and improve test effectiveness significantly. When compared with existing methods, experimental results on larger benchmark circuits of ISCAS'89 show that the proposed strategy can not only reduce significantly switching activity in circuits under test but also achieve high fault coverage.

• The Journal of the Korea Contents Association
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• v.5 no.4
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• pp.188-196
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• 2005

This paper presents a new test data compression and low power scan test method that can reduce test time and power consumption. A proposed method can reduce the scan-in power and test data volume using a modified scan cell reordering algorithm and hybrid adaptive encoding method. Hybrid test data compression method uses adaptively the Golomb codes and run-length codes according to length of runs in test data, which can reduce efficiently the test data volume compare to previous method. We apply a scan cell reordering technique to minimize the column hamming distance in scan vectors, which can reduce the scan-in power consumption and test data. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases. The proposed method showed an about a 17%-26% better compression ratio, 8%-22% better average power consumption and 13%-60% better peak power consumption than that of previous method.

• Korean Journal of Materials Research
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• v.27 no.11
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• pp.590-596
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• 2017

We demonstrated a CNT synaptic transistor by integrating 6,6-phenyl-C61 butyric acid methyl ester(PCBM) molecules as charge storage molecules in a polyimide(PI) dielectric layer with carbon nanotubes(CNTs) for the transistor channel. Specifically, we fabricated and compared three different kinds of CNT-based synaptic transistors: a control device with $Al_2O_3/PI$, a single PCBM device with $Al_2O_3/PI:PCBM$(0.1 wt%), and a double PCBM device with $Al_2O_3/PI:PCBM$(0.1 wt%)/PI:PCBM(0.05 wt%). Statistically, essential device parameters such as Off and On currents, On/Off ratio, device yield, and long-term retention stability for the three kinds of transistor devices were extracted and compared. Notably, the double PCBM device exhibited the most excellent memory transistor behavior. Pulse response properties with postsynaptic dynamic current were also evaluated. Among all of the testing devices, double PCBM device consumed such low power for stand-by and its peak current ratio was so large that the postsynaptic current was also reliably and repeatedly generated. Postsynaptic hole currents through the CNT channel can be generated by electrons trapped in the PCBM molecules and last for a relatively short time(~ hundreds of msec). Under one certain testing configuration, the electrons trapped in the PCBM can also be preserved in a nonvolatile manner for a long-term period. Its integrated platform with extremely low stand-by power should pave a promising road toward next-generation neuromorphic systems, which would emulate the brain power of 20 W.

• Tribology and Lubricants
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• v.12 no.3
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• pp.12-25
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• 1996

The friction and wear behaviors of ceramics against steels with lubricants were investigated and compared with those observed in air. Lubrications wbre done by a water and a commercial engine oil as received. The investigated ceramics were $Al_{2}O_{3}$, SiC, and $Si_{3}N_{4}$. Steels with 0.2 wt.% C were heat treated to obtain tempered structure. A cylinder-on-plate tribometer with rotated sliding motion was used to carry out the experiments. In the experiments reported here, the ranges of different testing speeds and loads were used. It was found that the friction and wear characteristics of tested pairs were significantly influenced by environments. In water and oil environments the wear of ceramics was reduced from 10$^{-6}$ g/s down to 10$^{-8}$ g/s in dry sliding at the same values of the frictional power which are the products of the friction coefficient, the load and the sliding speed. SiC showed excellent wear resistant behavior in water sliding, which was the lowest among tested ceramics, but it was, very poor in oils. In case of $Si_{3}N_{4}$, the wear rates were very low under oil environment, but the highest in water. The wear rates of $Al_{2}O_{3}$ were very low in both lubricating conditions at low values of the frictional power, but high at high values of the frictional power.

• Journal of KIISE:Software and Applications
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• v.35 no.5
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• pp.288-296
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• 2008

Software in defense domain requires high quality since defense specific characteristics. To assure high quality products, development and testing activities based on well defined process must be performed. If those activities cannot support software acquisition process, the quality of acquired software product is low and combat power decreases. In this paper, we propose MND-TMM(Ministry of National Defense-Testing Maturity Model), which can help enhance software quality through testing process improvements. This paper also introduces the contents of MND-TMM architecture. MND-TMM is constituted to reflect the characteristics of defense software, development process, and testing process so as to solve the problems associated with software testing. MND-TMM is comprised of 5 maturity levels and 4 categories which have number of related TPA(Testing Process Area)s. It is expected that MND-TMM can help assess testing maturity of defense software organizations and provides guidelines to improve software testing process.

• Journal of IKEEE
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• v.13 no.1
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• pp.77-86
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• 2009

A wavelet Electrocardiogram(ECG) detector and its analog-to-digital converter(ADC) for low-power implantable cardiac pacemakers are presented in this paper. The proposed wavelet-based ECG detector consists of a wavelet decomposer with wavelet filter banks, a QRS complex detector of hypothesis testing with wavelet-demodulated ECG signals, and a noise detector with zero-crossing points. To achieve high-detection performance with low-power consumption, the multi-scaled product algorithm and soft-threshold algorithm are efficiently exploited. To further reduce the power dissipation, a low-power ADC, which is based on a Successive Approximation Register(SAR) architecture with an on/off-time controlled comparator and passive sample and hold, is also presented. Our algorithmic and architectural level approaches are implemented and fabricated in standard $0.35{\mu}m$ CMOS technology. The testchip shows a good detection accuracy of 99.32% and very low-power consumption of $19.02{\mu}W$ with 3-V supply voltage.

• Journal of Electrical Engineering and Technology
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• v.9 no.2
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• pp.433-440
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• 2014

In this study, a method for the low-carbon active distribution system (ADS) planning is proposed. It takes into account the impacts of both network capacity and demand correlation to the renewable energy accommodation, and incorporates demand response (DR) as an available resource in the ADS planning. The problem is formulated as a mixed integer nonlinear programming model, whereby the optimal allocation of renewable energy sources and the design of DR contract (i.e. payment incentives and default penalties) are determined simultaneously, in order to achieve the minimization of total cost and $CO_2$ emissions subjected to the system constraints. The uncertainties that involved are also considered by using the scenario synthesis method with the improved Taguchi's orthogonal array testing for reducing information redundancy. A novel cuckoo search (CS) is applied for the planning optimization. The case study results confirm the effectiveness and superiority of the proposed method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.1
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• pp.81-90
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• 2004

The state assignment for a finite state machine greatly affects the delay, area, power dissipation, and testabilities of the sequential circuits. In order to improve the testabilities and power consumption, a new state assignment technique . based on m-block partition is introduced in this paper. By the m-block partition algorithm, the dependencies among groups of state variables are minimized and switching activity is further reduced by assigning the codes of the states in the same group considering the state transition probability among the states. In the sequel the length and number of feedback cycles are reduced with minimal switching activity on state variables. It is inherently contradictory problem to optimize the testability and power consumption simultaneously, however our new state assignment technique is able to achieve high fault coverage with less number of scan nfp flops by reducing the number of feedback cycles while the power consumption is kept low upon the low switching activities among state variables. Experiment shows drastic improvement in testabilities and power dissipation for benchmark circuits.