• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.42-47
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• 2020

In OFDM-based very high-speed communication systems, FFT/IFFT processor should have several properties of low-area and low-power consumption as well as high throughput and low processing latency. Thus, radix-2k MDF (multipath delay feedback) architectures by adopting pipeline and parallel processing are suitable. In MDF architecture, the feedback memory which increases in proportion to the input signal word-length has a large area and power consumption. This paper presents a feedback memory size reduction method of radix-22 MDF IFFT processor for OFDM applications. The proposed method focuses on reducing the feedback memory size in the first two stages of MDF architectures since the first two stages occupy about 75% of the total feedback memory. In OFDM transmissions, IFFT input signals are composed of modulated data and pilot, null signals. In order to reduce the IFFT input word-length, the integer mapping which generates mapped data composed of two signed integer corresponding to modulated data and pilot/null signals is proposed. By simulation, it is shown that the proposed method has achieved a feedback memory reduction up to 39% compared to conventional approach.

• KIISE Transactions on Computing Practices
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• v.22 no.7
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• pp.303-309
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• 2016

Recently, an increasing number of embedded processors such as ARM Mali begin to support GPGPU programming frameworks, such as OpenCL. Thus, GPGPU technologies that have been used in PC and server environments are beginning to be applied to the embedded systems. However, many embedded systems have different architectural characteristics compare to traditional PCs and low-power consumption and real-time performance are also important performance metrics in these systems. In this paper, we implement a parallel AES cryptographic algorithm for a modern embedded GPU using OpenCL, a standard parallel computing framework, and compare performance against various baselines. Experimental results show that the parallel GPU AES implementation can reduce the response time by about 1/150 and the energy consumption by approximately 1/290 compare to OpenMP implementation when 1000KB input data is applied. Furthermore, an additional 100 % performance improvement of the parallel AES algorithm was achieved by exploiting the characteristics of embedded GPUs such as removing copying data between GPU and host memory. Our results also demonstrate that higher performance improvement can be achieved with larger size of input data.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.6
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• pp.647-656
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• 2008

In this paper, we present interference power distribution results when radio frequency identification(RFID) and ubiquitous sensor network(USN) systems share the $908.5{\sim}914MHz$ frequency bands. Average interference powers are obtained by simulation and statistical analysis, respectively. Simulation results are then verified by statistical analysis. According to the number of interferers and the diameter of the protection area, the cumulative density functions(CDFs) of interference power are simulated under the various conditions. From the simulation results, the probability that both USN and RFID systems meet the required maximal interference power levels is 95 % on condition that there are 1 low revered RFID reader and several USN nodes and that the minimum distance between a RFID reader and an USN node is greater than 1 m. Our results can be used as an basic research for coexistence analysis of RFID and USN systems in the $908.5{\sim}914MHz$ frequency bands.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.95-103
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• 2007

Dynamic voltage scaling (DVS) is a well-known and effective power management technique. While there has been research on slack distribution, voltage allocation and other aspects of DVS, its effects on non-voltage-scalable devices has hardly been considered. A DC-DC converter plays an important role in voltage generation and regulation in most embedded systems, and is an essential component in DVS-enabled systems that scale supply voltage dynamically. We introduce a power consumption model of DC-DC converters and analyze the energy consumption of the system including the DC-DC converter. We propose an energy-optimal off-line DVS scheduling algorithm for systems with DC-DC converters, and show experimentally that our algorithm outperforms existing DVS algorithms in terms of energy consumption.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.9-14
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• 2013

This paper is designed frequency multiplier with low phase noise using DLL technique. The VCDL is designed using a differential structure to reduce common-mode noise. The proposed frequency multiplier is fabricated in a 65nm, 1.2V TSMC CMOS process, and the operating frequency range from 10MHz to 24MHz was measured. The SSB phase noise is measured to be -125dBc/Hz at 1MHz from 38.4MHz carrier. A total area of $0.032mm^2$were consumed in the chip, including the output buffer. Total current is 1.8mA at 1.2V supply voltage.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.3
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• pp.286-293
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• 2004

This paper presents the result of a study on the starter control for a turbo generator. Because a starter in gear box type turbo-generator system is composed of gearbox and brush DC motor, it should be replaced with High Speed Generator(HSG)) in HSG type Turbo-generator. There-ore, it is necessary to design a new starting algorithm and starter. In gearbox type system, brush DC motor is rotated to the designed speed using low voltage-high current battery power. After brush DC motor speed is increased to several times by gearbox, gas turbine engine can be rotated to designed starting speed. If we implement a starter with High Speed Generator(HSG), it is necessary to drive high-speed generator to high-speed motor. High-speed generator with permanent magnet on rotor has a low leakage inductance fur driving high-speed rotation, and it is necessary high DC link voltage for inverter when High-speed generator is driven to high speed. This paper presents result of development of the boost converter for converting high voltage DC from low battery voltage and design of the inverter for controlling a high frequency current to be injected to motor winding. Also, we show performance of the designed starter by driving the turbo generator.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.9
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• pp.11-17
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• 2006

We have theoretically investigated the effects of the interplay between the driving voltage of Mach-Zehnder(MZ) modulators and the bandwidth of low-pass filters(LPF) in 10[Gb/s] duobinary modulation systems. For the change of driving voltage ratios(driving voltage/switching voltage), the transmission performance has been evaluated over 200[km] of single-mode fiber(SMF) systems. For driving voltage ratios with smaller than 100[%], the transmission performance has been maintained and greatly affected by the bandwidth of LPFs than the driving voltage. For driving voltage ratios with larger than 100[%], the transmission performance has been degraded and is not sensitive to the bandwidth of LPFs. To see the limitation of driving voltage, we have reduced the driving voltage ratio to 50[%]. Our results suggest that 10[Gb/s] duobinary signals with driving voltage ratio with smaller than 100[%] have been transmitted over 200[km] SMF within 2[dB] power penalty without dispersion compensation. For the driving voltage ratio with 50[%], we have verified that the transmission performance was maintained.

• ETRI Journal
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• v.29 no.4
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• pp.421-429
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• 2007

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

• ETRI Journal
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• v.42 no.1
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• pp.54-66
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• 2020

Nowadays, the broad availability of cameras and embedded systems makes the application of computer vision very promising as a supporting technology for intelligent transportation systems, particularly in the field of vehicle tracking. Although there are several existing trackers, the limitation of using low-cost cameras, besides the relatively low processing power in embedded systems, makes most of these trackers useless. For the tracker to work under those conditions, the video frame rate must be reduced to decrease the burden on computation. However, doing this will make the vehicle seem to move faster on the observer's side. This phenomenon is called the fast motion challenge. This paper proposes a tracker called dynamic swarm particle (DSP), which solves the challenge. The term particle refers to the particle filter, while the term swarm refers to particle swarm optimization (PSO). The fundamental concept of our method is to exploit the continuity of vehicle dynamic motions by creating dynamic models based on PSO. Based on the experiments, DSP achieves a precision of 0.896 and success rate of 0.755. These results are better than those obtained by several other benchmark trackers.

• Journal of Electrical Engineering and Technology
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• v.13 no.6
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• pp.2227-2235
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• 2018

Under the current policies and compensation rules in South Korea, Photovoltaic (PV) generation supplier can maximize the profit by combining PV generation with Energy Storage System (ESS). However, the existing operational strategy of ESS is not able to maximize the profit due to the limitation of ESS capacity. In this paper, new ESS scheduling algorithm is introduced by utilizing the System Marginal Price (SMP) and PV generation forecasting to maximize the profits of PV generation supplier. The proposed algorithm determines the charging time of ESS by ranking the charging schedule from low to high SMP when PV generation is more than enough to charge ESS. The discharging time of ESS is determined by ranking the discharging schedule from high to low SMP when ESS energy is not enough to maintain the discharging. To compensate forecasting error, the algorithm is updated every hour to apply the up-to-date information. The simulation is performed to verify the effectiveness of the proposed algorithm by using actual PV generation and ESS information.