• ETRI Journal
• /
• v.43 no.5
• /
• pp.891-899
• /
• 2021

We propose a stray inductance extraction method on power modules of the few-kilovolts/several-hundred-amperes class using only low voltages and low currents. The method incorporates a double-pulse generator, a level shifter, a switching device, and a load inductor. The conventional approach generally requires a high voltage of more than half the power module's rated voltage and a high current of around half the rated current. In contrast, the proposed method requires a low voltage and low current environment regardless of the power module's rated voltage because the module is measured in a turn-off state. Both theoretical and experimental results are provided. A physical circuit board was fabricated, and the method was applied to three commercial power modules with EconoDUAL3 cases. The obtained stray inductance values differed from the manufacturer-provided values by less than 1.65 nH, thus demonstrating the method's accuracy. The greatest advantage of the proposed approach is that high voltages or high currents are not required.

• Proceedings of the KIEE Conference
• /
• 2006.04b
• /
• pp.344-346
• /
• 2006

In this paper, a novel algorithm for increasing the steady state efficiency during light load operation of the induction generator that integrated with a wind power generation system is presented. The proposed algorithm based on the flux level reduction, where the flux level is estimated using Support-Vector -Machines for regression (SVR) for the optimum d-axis current of the generator. SVR is trained off-line to estimate the unknown mapping between the system's inputs and outputs, and then is used online to calculate the optimum d-axis current for minimizing generator loss. The experimental results show that SVR can define the flux-power loss accurately and determine the optimum d-axis current value precisely. The loss minimization process is more effective at low wind speed and the percent of power saving can approach to 40%.

• Ocean and Polar Research
• /
• v.23 no.2
• /
• pp.133-139
• /
• 2001

Ocean currents estimated from sea height anomalies derived from inter-calibrated TP/ERS are compared with daily mean currents measured with satellite-tracked drifters. The correlation coefficient between the geostrophic current from TP/ERS and surface current at 15 m depth from drifter tracks was found to be about 0.5. Due to the limitation of satellite ground tracks, small scale eddies less than 80 km are poorly resolved from TP/ERS. One of the interesting results of this study is that coastal currents along the eastern coast of Korea were well reproduced from sea height anomalies when the coastal currents were developed in association with eddies near the South Korean coast. The eddy kinetic energy (EKE) estimated from drifters, TP/ERS, and a numerical model are also compared. The EKE estimated from drifters was about 22 % higher than EKE calculated from TP/ERS. The pattern of low EKE level in the northern basin and high EKE level in the southern East Sea is shown in the EKE estimates derived from both the drifters and TP/ERS.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.10 no.1
• /
• pp.55-60
• /
• 2010

For battery-powered device applications, which grow rapidly in the electronic market today, low-power becomes one of the most important design issues of CMOS VLSI circuits. A multi-VDD system, which uses more than one power-supply voltage in the same system, is an effective way to reduce the power consumption without degrading operating speed. However, in the multi-VDD system, level converters should be inserted to prevent a large static current flow for the low-to-high conversion. The insertion of the level converters induces the overheads of power consumption, delay, and area. In this paper, we propose a new level converter which can provide the level up/down conversions for the various input and output voltages. Since the proposed level converter uses only one power-supply voltage, it has an advantage of reducing the complexity in physical design. In addition, the proposed level converter provides lower power and higher speed, compared to existing level converters.

• Journal of the Korean Society of Manufacturing Process Engineers
• /
• v.13 no.4
• /
• pp.56-68
• /
• 2014

This paper presents an experiment on the modeling, analysis, prediction and optimization of machining parameters used during the turning process of the low-carbon steel known as ST40. The parameters used to develop the model are the cutting speed, the feed rate, and the depth of the cut. The experiments were carried out under various conditions, with three level of parameters and two different treatments for each level (with and without a lubricant), to determine the effects of the parameters on the surface roughness and electric current consumption. These effects were investigated using response surface methodology (RSM). A second-order model is used to predict the values of the surface roughness and the electric current consumption from the results of experiments which collected preliminary data. The results of the experiment and the predictions of the surface roughness and electric current consumption under both treatments were found to be nearly identical. This result shows that the feed rate is the main factor that influences the surface roughness and electric current consumption.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.7 no.4
• /
• pp.215-220
• /
• 2007

Leakage current of CMOS circuits has become a major factor in VLSI design these days. Although many circuit-level techniques have been developed, most of them require significant amount of designers' effort and are not aligned well with traditional VLSI design process. In this paper, we focus on technology mapping, which is one of the steps of logic synthesis when gates are selected from a particular library to implement a circuit. We take a radical approach to push the limit of technology mapping in its capability of suppressing leakage current: we use a probabilistic leakage (together with delay) as a cost function that drives the mapping; we consider pin reordering as one of options in the mapping; we increase the library size by employing gates with larger gate length; we employ a new flipflop that is specifically designed for low-leakage through selective increase of gate length. When all techniques are applied to several benchmark circuits, leakage saving of 46% on average is achieved with 45-nm predictive model, compared to the conventional technology mapping.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.5 no.4
• /
• pp.367-370
• /
• 2004

We fabricated SiGe BiCMOS devices, which are important for ultra high speed RF IC chips, by employing $0.35\mu{m}$ CMOS process. To meet with the requirement of low noise level with linear base leakage current at low VBE region, we try to minimize polysilicon/ silicon interface traps by optimizing capping silicon thickness and EDR(emitter drive-in RTA) temperature. We employed $200\AA$and $300\AA$-thick capping silicon, and varied the EDR process condition at temperature of $900-1000^\circ{C}$, and time of 0-30 sec at a given capping silicon thickness. We investigated current gain behavior at each process condition. We suggest that optimum EDR process condition would be $975^\circ{C}$-30 sec with $300\AA$-thick capping silicon for proposed $0.35\mu{m}$-SiGe HBT devices.

• Journal of Power Electronics
• /
• v.19 no.6
• /
• pp.1477-1485
• /
• 2019

This paper proposes an effective model predictive current control (MPCC) that involves using 10 virtual voltage vectors to reduce the current harmonics and common-mode voltage (CMV) for a two-level five-phase voltage source inverter (VSI). In the proposed scheme, 10 virtual voltage vectors are included to reduce the CMV and low-order current harmonics. These virtual voltage vectors are employed as the input control set for the MPCC. Among the 10 virtual voltage vectors, two are applied throughout the whole sampling period to reduce current ripples. The two selected virtual voltage vectors are based on location information of the reference voltage vector, and their duration times are calculated using a simple algorithm. This significantly reduces the computational burden. Simulation and experimental results are provided to verify the effectiveness of the proposed scheme.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.1
• /
• pp.180-184
• /
• 2013

In this paper, a low power antenna switch controller IC is designed using a silicon-on-insulator (SOI) CMOS technology. To improve power handling capability and harmonic distortion performance of the antenna switch, the proposed antenna switch controller provides 3-state logic level such as +VDD, GND, and -VDD for the gate and body of switch of FETs according to decoder signal. By employing input-coupled current ring oscillator and hardware efficient level shifter, the proposed controller greatly reduces power consumption and hardware complexity. It consumes 135 ${\mu}A$ at a 2.5 V supply voltage in active mode, and occupies $1.3mm{\times}0.5mm$ in area. In addition, it shows fast start-up time of 10 ${\mu}s$.

• Journal of Families and Better Life
• /
• v.24 no.1 s.79
• /
• pp.193-207
• /
• 2006

The purpose of this study was to analyze middle-aged salaried workers' retirement plans and the factors that affect the plans. The main point of this study was to compare male workers with female workers on their economic preparation and health care plans. The major findings were as follows; First, middle-aged salaried workers perceived their level of economic retirement plan to be relatively low. Second, the factors the affected the level of economic preparation for post-retirement were their current subjective economic level, age, household assets and debts, economic and health problems expected in their future elderly life, and savings and assets reserved for their elderly life. Third, the factors that affected whether to put aside savings for elderly life or not were age, current subjective economic level, capital assets, and savings and assets reserved for their elderly life. Fourth, the level of preparation for post-retirement health care depended on health problems expected in their elderly life, current subjective economic level, locus of control, job, and expected retirement age. Overall, the factors that affect male salaried workers' economic and health care plans were different from those of female salaried workers. From the findings, it can be concluded that the middle-aged salaried workers' level of economic retirement plans was different from that of their health care plans. Also, male salaried workers' level of retirement plan were different from that of female workers.