• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.15 no.12
• /
• pp.1021-1026
• /
• 2002

As the development of semiconductor process technology continue to advance, ICs continue their trend toward higher performance low power system-on-chip (SOC). These circuits require on board multi power supply. In this paper, a 0.5 ㎛ dual date oxide CMOS Process technology for multi-power application is demonstrated. 5 V and 20 V devices fabricated by proposed process is measured. From 5 V devices using dual gate precess, we got almost the same characteristics as are obtained from standard 5 V devices. And the characteristics of the 20 V device demonstrates that 3 ㎛ devices with minimum gate length are available without reliability degradation. Electrical parameters in minimum 3 ㎛ devices are 520 ㎂/㎛ current density, 120 ㎷ DIBL, 24 V BV for NMOS and ,350 ㎂/㎛ current density, 180 ㎷ DIBL, 26 V BV for PMOS, respectively.

• Transactions of the Korean Society of Mechanical Engineers B
• /
• v.28 no.7
• /
• pp.857-862
• /
• 2004

HCCI engines take advantage of high compression ratio and heat release rate, they exhibit high efficiency in compression ignition engines. HCCI engines also utilize a lean air/fuel ratio resulting in low emissions of NOx and particulate matter(PM). The objective of this research is to determine the effects of EGR rate on the combustion processes of HCCI. For this purpose, a 4-cylinder, compression ignition engine was converted into a HCCI engine, and a heating device was installed to raise the temperature of the intake air and also to make it more consistent. In addition, a pressure sensor was inserted into each of the cylinders to investigate the differences in characteristics among the cylinders.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.9
• /
• pp.85-95
• /
• 2004

As the design complexity increases, it is a major problem that the size of test pattern is large and power consumption is high in scan, especially system-on-a-chip(SoC), with the automatic test equipment(ATE). Because static compaction of test patterns heads to higher power for testing, it is very hard to reduce the test pattern volume for low power testing. This paper proposes an efficient compression/decompression algorithm based on run-length coding for reducing the amount of test data for low power testing that must be stored on a tester and be transferred to SoC. The experimental results show that the new algorithm is very efficient by reducing the memory space for test patterns and the hardware overhead for the decoder.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.3
• /
• pp.496-502
• /
• 2006

The complexity of IC has rapidly increased as VLSI fabrication technology has grown up quickly. This paper proposes verification methods for data conflicts and protocol between IPs for SoC with coverage metrics. The high-level events is defined to cooperation between blocks or process statement in HDL, or a sequence of performing a job compared to low-level event. They are classified into two categories, resource conflicts and protocol or specification-dependent conflicts. And two coverage metrics used for code coverage in low-level event are proposed to verify the hish-level events. The events of resource conflicts can be detected by using statement coverage metric if global signal or variable has flags in a testbench program, and protocol-dependent events can be checked by data flow metric or path metric.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.2
• /
• pp.321-327
• /
• 2006

This paper presents low power and high frequency design of instructions using ad-hoc techniques at transistor level for full custom and semi-custom ASIC(Application Specific Integrated Circuit) designs. The proposed design has been verified at high level using Verilog-HDL and simulated using ModelSim for the logical correctness. It is then observed at the layout level using LASI using $0.25{\mu}m$ technology and analyzed for timing characteristic under Win-spice simulation environment. The result shows the significant reduction up to $35\%$ in the power consumption by any general purpose processor like RISC or CISC. A significant reduction in the propagation delay is also observed. increasing the frequency for the fetch and execute cycle for the CPU, thus increasing the overall frequency of operation.

• Journal of Nutrition and Health
• /
• v.34 no.5
• /
• pp.493-498
• /
• 2001

To investigate the effects of Ixeris sonchifolia Hance diets on serum and hepatic lipid levles and enzyme activities in rats administered with ethanol chronically, Sprague-Dawley male rats were AIN-76 diet(control), control diet plus ethanol, control plus Ixeris sonchifolia Hance diet, or control plus Ixeris sonchifolia Hance diet plus ethanol for 30 days. Ixeris sonchifolia Hance diets significantly decreased the serum total cholesterol, triglyceride, LDL-cholesterol, and GOT levels that were increased due to the chronic ethanol administration. In addition, Ixeris sonchifolia Hance diets significantly decreased the liver triglyceride and total lipid levels that were increased due to the ethanol administration. The present findings, combined with previous data showing differences in the effects of cabbage diets having a high or a low level of GABA on the lipid levels and the serum Y-GPT activity of rats(Cha and OH[2000] J. Korean Soc. Food Sci. Nutr. 29, 500-505) raise the possibility that GABA in plants could have a nytraceutical role in the recovery of chronic alcohol-related diseases. (Korean J Nutrition 34(5) : 493∼498, 2001)

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.105-108
• /
• 2001

4 32-bit RISC core is designed for embedded application and DSP. This processor offers low power consumption by fully static operation and compact code size by efficient instruction set. Processor performance is improved by wing conditional instruction execution, block data transfer instruction, multiplication instruction, bunked register file structure. To support compact code size of embedded application, It is capable cf executing both 16-bit instructions and 32-bit instruction through mixed mode instruction conversion Furthermore, for fast MAC operation for DSP applications, the processor has a dedicated hardware multiplier, which can complete a 32-bit by 32-bit integer multiplication within seven clock cycles. These result in high instruction throughput and real-time interrupt response. This chip is implemented with 0.35${\mu}{\textrm}{m}$, 4- metal CMOS technology and consists of about 50K gate equivalents.

• Journal of the Korean Solar Energy Society
• /
• v.31 no.5
• /
• pp.119-125
• /
• 2011

In this paper, we have studied about minimizing the Energy Storage System (ESS) capacity for mitigating the fluctuation of Wind Turbine Generation System (WTGS) by using Electric Double Layer Capacitor (EDLC) and Battery Energy Storage System (BESS). In this case, they have some different characteristics: The EDLC has the ability of generating the output power at high frequency. Thus, it is able to reduce the fluctuation of WTGS in spite of high cost. The BESS, by using Li-Ion battery, takes the advantage of high energy density, however it is limited to use at low frequency response. To verify the effectiveness of the proposed method, simulations are carried out with the actual data of 2MW WTGS in case of worst fluctuation of WTGS is happened. By comparing simulation results, this method shows the excellent performance. Therefore, it is very useful for understanding and minimizing the ESS capacity for mitigating the fluctuation of WTGS.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.20 no.2
• /
• pp.160-166
• /
• 2015

This study proposes an improved cell balancing circuit for fast equalization among lithium-ion (Li-ion) batteries. A simple voltage sensorless charge balancing circuit has been proposed in the past. This cell balancing circuit automatically transfers energy from high-to low-voltage battery cells. However, the circuit requires a switch with low on-resistance because the balancing speed is limited by the on-resistance of the switch. Balancing speed decreases as the voltage difference among the battery cells decrease. In this study, the balancing speed of the cell balancing circuit is enhanced by using the auxiliary circuit, which boosts the balancing current. The charging current is determined by the nominal battery cell voltage and thus, the balancing speed is almost constant despite the very small voltage differences among the batteries. Simulation results are provided to verify the validity of the proposed cell balancing circuit.

• Asian Pacific Journal of Cancer Prevention
• /
• v.16 no.1
• /
• pp.307-314
• /
• 2015

Background: Bladder cancer is among the five most common malignancies worldwide. Altered expression of suppressor of cytokine signaling -3 (SOCS-3) has been implicated in various types of human cancers; however, its role in bladder cancer is not well established. Aim: The present study was undertaken to investigate the mRNA expression of SOCS-3 in normal and cancerous bladder tissue and to explore its correlation with urinary levels of some proinflammatory cytokines, cytokeratin-18 (CK -18) and with tumor histopathological grading, in order to evaluate their role as potential diagnostic markers. Materials and Methods: SOCS3 mRNA expression levels were evaluated using quantitative real time PCR. Urinary levels of interleukins 6 and 8 were estimated by enzyme linked immunosorbent assay (ELISA). Cytokeratin-18 expression was analyzed by immuunohistochemistry then validated by ELISA. Results: SOC3 m RNA expression levels were significantly lower in high grade urothelial carcinoma ($0.36{\pm}0.12$) compared to low grade carcinoma ($1.22{\pm}0.38$) and controls ($4.08{\pm}0.88$), (p<0.001). However, in high grade urothelial carcinoma the urinary levels of IL-6, IL-8, total CK-18($221.33{\pm}22.84pg/ml$, $325.2{\pm}53.6pg/ml$, $466.7{\pm}57.40U/L$ respectively) were significantly higher than their levels in low grade carcinoma ($58.6{\pm}18.6pg/ml$, $58.3{\pm}50.2pg/ml$, $185.5{\pm}60.3U/L$ respectively) and controls ($50.9{\pm}23.0pg/ml$, $7.12{\pm}2.74pg/ml$, $106.7{\pm}47.3U/L$ respectively), (p<0.001). Conclusions: Advanced grade of urothelial bladder carcinoma is significantly associated with lowered mRNA expression of SOC3 as well as elevated urinary levels of proinflammatory cytokines and CK-18. Furthermore, our results suggested that urinary IL-8, IL-6 and CK-18 may benefit as noninvasive biomarkers for early detection as well as histopathological subtyping of urothelial carcinoma.