1 |
Edmund M. Clarke, Orna Grumberg, Doron A. Peled, Model Checking, MIT Press, 2000
|
2 |
Kevin Skahill, 'A Designer's guide to VHDL design and verification', Electronic design, pp. 149-152, Feb. 19, 1996
|
3 |
W. Howden, 'Confidence-based reliability and statistical coverage estimation', ISSRE'97, pp 283-291, Nov, 1997
|
4 |
Martin Abraham, et al, 'Optimize ASIC testsuite using code coverage analysis', EDN, pp. 149-152, Mat 21, 1998
|
5 |
Brian Barrera, 'Code coverage analysis-essential to a safe design', Electronic Engineering, pp 41-43, Nov. 1998
|
6 |
Jen- Tien Yen and Qichao Richard Yin, 'Multiprocessing Design Verification Methodology for Motorola MPC74XX PowerPC Microprocessor,' DAC, pp 718-723, 2000
|
7 |
Wooseung Yang, Moo-Kyeong Chung and ChongpMin Kyung, 'Current Status and Challenges of Soc Verification for Embedded Systems Market,' IEEE, pp. 213-216, 2003
|
8 |
Janick Bergeron, Writing Testbenches : Functional Verification of HDL models, 2nd edition, Kluwer Academic Publishers, 2003
|
9 |
Qiushang Zhang and Ian G. Harris, 'A Data Flow Fault Coverage Metric For Validation of Behavioral HDL Descriptions', ICCAD, pp. 369-372, 2000
|
10 |
Jim Lipman, 'Covering your HDL chip-design bets', EDN, pp 65-74. Oct. 1998
|
11 |
Gilly Nativ, et. al, 'Cost evaluation of coverage directed test generation for the IBM Mainframe', ITC, pp 793-801, 2001
|
12 |
Michael Keating and Pierre Bricaud, Reuse Methodology Manual, Kluwer Academic Publishers, 1998
|
13 |
Amjad Hajjar and Tom Chen, 'An Accurate Forecasting Model for Behavioral Model Verification,' Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications, 2002
|
14 |
Rolf Drechsler and Bernd Becker, Binary Design Diagrams : Theory and Implementation, Kluwer Academic Publishers, 1998
|
15 |
Daniel Geist, et. al, 'A Methodology for the verification of on a System on chip', DAC, pp 574-579, 1999
|
16 |
Kangchul Kim, 'Efficient methods for reducing clock cycles in VHDL model verificatoin,' Journal of Electronics Engineers of Korea, V.40-SD, pp39-45, Dec. 2003
|
17 |
B. Dickinson, S. Shaw, 'Software techniques applied to VHDL design', New Electronics, N9, pp 63-65, May 1995
|
18 |
Cindy Eisner, et ai, 'A Methodology for Formal Design of Hardware Control with Application to Cache Coherence Protocols,' DAC, pp 724-729, 2000
|
19 |
John D. Carpinelli, Computer Systems Organization and Architecture, Addison Wesley, 2000
|
20 |
Kazuyoshi Kohno, Nobu Matsumoto, 'A New Verification Methology for Complex Pipeline Behavior,' DAC, pp. 816-821, 2001
|
21 |
Hoon Choi, Byeongwhee Yun, Yuntae Lee, and Hyungglae Roh, 'Model Checking of S3C2400X Industrial Embedded SoC Product,' DAC, pp. 611-616. 2001
|