• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.6 s.360
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• pp.1-8
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• 2007

In wireless sensor network which uses limited battery, power consumption is very important factor for the survivality of the system. By using low-power communication to reduce power consumption, error rate is increased in typical conditions. This paper analyzes power consumption of specific error control coding (ECC) implementations. With identical link quality, ECC provides coding gain which save the power for transmission at the cost of computing power. In sensor node, transmit power is higher than computing power of Micro Controller Unit (MCU). In this paper, Viterbi algerian is applied to the low-transmit-power sensor networks in terms of network power consumption. Practically, Viterbi algorithm presents 20% of reduction of re-transmission in compared with Auto Repeat Request (ARQ) system. Furthermore, it is observed that network power consumption is decreased by almost 18%.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.5 s.311
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• pp.1-7
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• 2006

This paper presents experimental instruction-level current consumption model for low power microcontroller ATmega128. The accessibility of instruction for internal memory decides power consumption of the microcontroller as much as 17% of difference between access instruction and non-access instruction. The power consumption for the given program will be increased in the proportional to the ratio of memory access instruction and lower level memory access in the hierarchy. Throughout the current consumption model, the power consumption can be predicted and optimized in the direction of reducing the frequency memory access. Also, the various optimization methods are introduced in terms of software and hardware viewpoints.

• Journal of IKEEE
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• v.12 no.1
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• pp.27-33
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• 2008

The demand of wireless communication is increased rapidly due to the development of wireless communication systems, and many people have the great interest about the "RF system". The trend of the RF audio system is to design the system with less power consumption. In this paper, we explain the Software Algorithm Design of RF systems that is suitable for low power consumption.

• Journal of the Korean Institute of Intelligent Systems
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• v.20 no.6
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• pp.793-798
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• 2010

In this paper we propose a low-power walking compensation method for biped robot based on consumption energy analysis. Firstly, basic walking motions that can reduce energy consumption of robot movements are implemented based on consumption energy analysis according to robot axes. We define knee bent motion as a basic walking motion. It can improve energy consumption and motion stability by lowering center of gravity of the biped robot. We analyze consumption energy of left and right leg of the robot using motor currents and propose a compensation method of walking motions to reduce unbalance of consumption energy between left leg and right leg. It can also improve energy consumption and walking stability of the robot. The proposed low-power compensation method based on consumption energy analysis is verified by walking experiments of a small biped robot with an embedded system.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.1-10
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• 1999

A low power concumption 2.4 GHz one-chip transceiver MMIC was designed and fabricated using $1.0\mu\textrm{m}$ ion-implantation MESFET process and packaged on a 24 lead SSOP. In the transmitter mode, it revealed conversion gain of 7.5 dB, output IP3 of -3.5 dBm, and noise figure of 3.9 dB at 2.44 GHz with 3.9 mA current consumption. In the receiver mode, it revealed voltage sensitivity of 6.5 mV/$\mu\$W with 2 .0 mA current consumption. Comparing the fabricated MMIC with the results of MMICs reported elsewhere, it was shown that the fabricated MMIC had good performance. The low power consumption 2.4 GHz transceiver MMIC is expected to be used for various applications such as wireless local area networks, wireless local loops and RFID tags in ISM-band.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.6
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• pp.1145-1152
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• 2019

In this paper, a low power current mode 12-bit ADC(: Analog to Digital Converter) is proposed to mix digital circuits and analog circuits with the advantages of low power consumption and high speed operation. The proposed 12 bit ADC is implemented by using 4-bit ADC in a cascade structure, so its power consumption can be reduced, and the chip area can be reduced by using a conversion current mirror circuit. The proposed 12-bit ADC is SK Hynix 350nm process, and post-layout simulation is performed using Cadence MMSIM. It operates at a supply voltage of 3.3V and the area of the proposed circuit is 318㎛ x 514㎛. In addition, the ADC shows the possibility of operating with low power consumption of 3.4mW average power consumption in this paper.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.159-165
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• 2016

Recently, active efforts are being made for future Si CMOS technology by various researches on emerging devices and materials. Capability of low power consumption becomes increasingly important criterion for advanced logic devices in extending the Si CMOS. In this work, a junctionless field-effect transistor (JLFET) with ultra-thin poly-Si (UTP) channel is designed aiming the sub-10-nm technology for low-power (LP) applications. A comparative study by device simulations has been performed for the devices with crystalline and polycrystalline Si channels, respectively, in order to demonstrate that the difference in their performances becomes smaller and eventually disappears as the 10-nm regime is reached. The UTP JLFET would be one of the strongest candidates for advanced logic technology, with various virtues of high-speed operation, low power consumption, and low-thermal-budget process integration.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.1
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• pp.1-9
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• 2007

Since data caches used in modern embedded processors consume significant fraction of total processor power up to 40%, embedded processors need power-efficient high performance data caches. This paper proposes a prefetching data cache structure which pursuing low power consumption. We added tag history table on existing data cache structure which includes hardware unit for data prefetching so that reduce the number of parallel lookup on tag memory. This strategic cache structure remarkably reduces power consumption for parallel tag lookup. Experimental results show that the proposed cache architecture induce low power consumption while maintain the same cache performance.

• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.2
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• pp.75-80
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• 2014

Energy consumption of sensor nodes is minimized because it has limited energy generator in wireless sensor network. Electronic shelf label system is one of application fields using wireless sensor networks. Battery size of small apparatus for displaying price is restricted. Therefore its current consumption have to be minimized. Furthermore the method for minimization of peak current would be considered because life cycle of coin battery used to display or RF is vulnerable to intensity of drain current. In this paper, we analyze current consumption pattern of low-power electronic shelf label system. Then we propose the method for minimization of current consumption by modification of software and hardware. Current consumption of the system using proposed method are approximately 15 to 20 percent lower than existing system and the life cycle of the system is approximately 10 percent higher than existing system.

• ETRI Journal
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• v.30 no.3
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• pp.451-460
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• 2008

Recently, the power consumption of integrated circuits has been attracting increasing attention. Many techniques have been studied to improve the power efficiency of digital signal processing units such as fast Fourier transform (FFT) processors, which are popularly employed in both traditional research fields, such as satellite communications, and thriving consumer electronics, such as wireless communications. This paper presents solutions based on parallel architectures for high throughput and power efficient FFT cores. Different combinations of hybrid low-power techniques are exploited to reduce power consumption, such as multiplierless units which replace the complex multipliers in FFTs, low-power commutators based on an advanced interconnection, and parallel-pipelined architectures. A number of FFT cores are implemented and evaluated for their power/area performance. The results show that up to 38% and 55% power savings can be achieved by the proposed pipelined FFTs and parallel-pipelined FFTs respectively, compared to the conventional pipelined FFT processor architectures.