• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2011년도 추계학술발표대회
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• pp.44-47
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• 2011

In this paper, we propose context-aware based on Low Power Sensing Algorithm. The proposed sensing algorithm reduces power consumptions using low-power sensing algorithms and low-power sensing protocols. Experimental results show that the average power consumption of the proposed method is up to half consumption that of the conventional method.

• 디지털산업정보학회논문지
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• 제5권3호
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• pp.69-75
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• 2009

In this paper, we proposed CPLD low power algorithm using reduce glitch power consumption. Proposed algorithm generated a feasible cluster by circuit partition considering the CLB condition within CPLD. Glitch removal process using delay buffer insertion method for feasible cluster. Also, glitch removal process using same method between feasible clusters. The proposed method is examined by using benchmarks in SIS, it compared power consumption to a CLB-based CPLD low power technology mapping algorithm for trade-off and a low power circuit design using selective glitch removal method. The experiments results show reduction in the power consumption by 15% comparing with that of and 6% comparing with that of.

• 한국연소학회:학술대회논문집
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• 한국연소학회 2013년도 제46회 KOSCO SYMPOSIUM 초록집
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• pp.129-132
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• 2013

The low rank coal combustion and biomass-coal co-firing characteristics were reviewed on this study for the power plant construction. The importance of using low rank coal(LRC) for power plant is increasing gradually due to power generation economy and biomass co-firing is also concentrated as power source because it has carbon neutral characteristics to reduce green-house effect. The combustion characteristics of low rank coal and biomass for a 310MW coal firing power plant and a 100MW biomass and coal co-firing power plant were studied to apply into actual power plant design and optimized the furnace and burner design.

• ETRI Journal
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• 제44권3호
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• pp.491-503
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• 2022

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short-channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large-scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor-level input-controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low-power ICS approach is extensively discussed to verify its importance in low-power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low-power and high-speed techniques at a 22-nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5-inverters.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제16권5호
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• pp.1735-1754
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• 2022

The reliability and performance of WiFi need optimization because of the rising number of WiFi users day by day. A highlighted point is saving power while transmitting and receiving packets using WiFi devices. Wake-on-Wlan (WoW) is also implemented to improve energy consumption, but it also needs betterment. This paper will introduce universal ideas to transmit and receive packets using low-power technology like Bluetooth or BLE (Bluetooth low energy). While looking for power-saving ways in this research, WiFi connection and maintenance also take care using lesser power-consuming technology. Identifying different use-cases where low power technology can help save energy and maintain 802.11 connection is part of the research. In addition, the proposed method discuss energy saving with unicast and broadcast/multicast data. Calculation of power-saving and comparison with standalone WiFi usage clearly shows the effectiveness of the proposed method.

• 정보처리학회논문지A
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• 제14A권3호
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• pp.147-150
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• 2007

본 논문에서는 작은 점유면적과 저 전력 소모 특성을 갖도록 CPL(Complementary Pass-Transistor Logic) 논리구조의 전가산기에 저 전압 스윙 기술을 적용하여 16$\times$16 비트 병렬 곱셈기를 설계하였다. 회로구성상 CPL 논리구조는 CMOS 논리구조에 비해 NMOS 트랜지스터만을 사용하기 때문에 작은 면적을 소비한다. 저 전압 스윙 기술은 회로에 공급되는 전압보다 낮은 전압 레벨에서 출력 동작을 하여 전력 소모를 감소시키는 기술이다. 본 논문에서는 전가산기의 출력 단에 사용되는 인버터에 저 전압 스윙 기술을 적용하여 저 전력 소모 특성을 갖는 16$\times$16 비트 병렬 곱셈기를 설계하였다 설계한 회로는 17.3%의 전력 소모 감소와 16.5%의 전력소모와 지연시간의 곱(Power Delay) 감소가 이루어졌다.

• 대한전자공학회논문지SD
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• 제42권2호
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• pp.41-48
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• 2005

본 논문은 기존의 CVSL 전가산기 회로 내부에 Low-Swing 기술의 특성을 갖도록 NMOS 트랜지스터를 추가하여 감소된 출력전압으로 동작하는 CVSL 전가산기를 제안하였다. 또한 제안한 Low-Swing CVSL 전가산기를 이용하여 $8\times8$ 병렬 곱셈기를 구성한 후 회로의 성능을 평가하였다. 본 논문에서 제안한 Low-Swing CVSL 전가산기 회로는 $13.1\%$의 전력감소와 $14.3\%$의 전력소모와 지연시간의 곱(power-delay-product) 감소가 이루어졌다 Hynix $0.35{\mu}m$ 표준 CMOS 공정을 사용하여 HSPICE로 시뮬레이션하고 그 동작 특성을 검증하였다.

• 한국HCI학회:학술대회논문집
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• 한국HCI학회 2008년도 학술대회 1부
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• pp.280-285
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• 2008

ZigBee는 저전력 저속 근거리 무선 통신 프로토콜로서 센서 네트워크에 많은 적용이 되는 프로토콜이다. ZigBee가 PAN을 구성하는 방법은 Beacon Enabled PAN과 Non Beacon Enabled PAN의 두 가지가 존재 한다. Non Beacon Enabled PAN에서 데이터 전송방식은 End-Device가 원하는 시점에 Active 상태에 진입하여 데이터를 보내는 방법으로 저전력을 지원한다. 그러므로 Router는 End-Device가 데이터를 보내는 시간을 정확히 알 수 없게된다. 이런 문제를 해결하기 위해서 Router는 항상 Active 상태로 존재해야 한다. 이로 인해 Non Beacon Enabled PAN을 사용하는 센서 네트워크에서 Router는 별도의 상시 전원을 공급 받아야한다. 그러나 Non Beacon Enabled PAN의 ZigBee Router가 건전지와 같은 한정적인 전력 공급원을 가지게 되는 상황에서는 안정적인 네트워크 구축이 불가능하게 된다. 본 논문에서는 이를 해결하기 위해서 PAN Time을 통한 네트워크 동기화를 사용한 저전력 알고리즘을 제안한다. End-Device는 PAN Time을 사용하여 PAN의 동기화를 수행하며, PAN Time을 통해 Router의 저전력 진입을 지원한다.

• Journal of Power Electronics
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• 제10권3호
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• pp.219-227
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• 2010

Telecom supplies need to conform to low Total Harmonic Distortion (THD) and high Power Factor (PF) as per IEC 61000-3-2 and IEEE 519-1992 standards. These high rating power supplies use a three phase utility in which low THD and high PF are realized via various passive and active wave shaping schemes. In this paper, a new design for three phase telecom power supplies is presented with circuit parameter values optimized for high performance in terms of a low THD, high PF, low ripple and high line and load regulation using a suitable combination of various strategies. The performance of the power supply is validated by extensive simulations.

• KEPCO Journal on Electric Power and Energy
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• 제6권4호
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• pp.405-411
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• 2020

In this paper, we designed the COS MEMS system for sensing the falling detection and explosive noise of fuse link in COS (Cut Out Switch) installing on the power distribution. This system analyzed the failure characteristics and an instantaneous breakdown of power distribution. Therefore, our system strengths the industrial competence and guaranties the stable power supply. In this paper, we applied BLE (Bluetooth Low Energy) technology which is suitable protocol for low data rate, low power consumption and low-cost sensor applications. We experimented with LSM6DSOX which is system-in-module featuring 3 axis digital accelerometer and gyroscope boosting in high-performance mode and enabling always-on low-power features for an optimal motion for the COS fuse holder. Also, we used the MP34DT05-A for gathering an ultra-compact, low power, omnidirectional, digital MEMS microphone built with a capacitive sensing element and an IC interface. The proposed COS MEMS system is developed based on nRF52 SoC (System on Chip), and contained a 3-axis digital accelerometer, a digital microphone, and a SD card. In this paper of experiment steps, we analyzed the performance of COS MEMS system with gathering the accelerometer raw data and the PDM (Pulse Data Modulation) data of MEMS microphone for broadcasting the failure of COS status.