• Title/Summary/Keyword: Low IMD

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A Highly Linear Self Oscillating Mixer Using Second Harmonic Injection (2차 고조파 주입을 사용한 고 선형성의 자체 발진 혼합기)

  • Kim, Min-Hoe;Cho, Choon-Sik;Lee, Jae-Wook
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.23 no.6
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    • pp.682-690
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    • 2012
  • In this paper, a highly linear self oscillating mixers(SOM) using second harmonic injections are presented. The H-slot defected ground structure(DGS) is designed as a balanced resonator for oscillation in the proposed SOM. Since the H-slot DGS resonator achieves a high Q factor, it is a suitable structure to provide low phase noise for the oscillator. The single balanced mixer is utilized in this work and it provides good LO-RF isolation since balanced LO signals are suppressed at the RF input port. In order to inject the second harmonic of the IF, we propose two different methods using feedback loops. In the first method, IF achieves a 3.08 dB conversion gain at 226 MHz with input power of -20 dBm at 5 GHz RF input signal. The IF achieves 2 dB conversion gain at 423 MHz with the input power of -20 dBm at 5.2 GHz RF input signal in the second method. The measured IMD3s are 61.8 dB and 65 dB for the each method. These SOMs present improved linearity compared to that without the second harmonic injection because IMD3s are improved by 18. dB and 21 dB for each method.

Effect of a Multi-Step Gap-Filling Process to Improve Adhesion between Low-K Films and Metal Patterns

  • Lee, Woojin;Kim, Tae Hyung;Choa, Yong-Ho
    • Korean Journal of Materials Research
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    • v.26 no.8
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    • pp.427-429
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    • 2016
  • A multi-step deposition process for the gap-filling of submicrometer trenches using dimethyldimethoxysilane (DMDMOS), $(CH_3)_2Si(OCH_3)_2$, and $C_xH_yO_z$ by plasma enhanced chemical vapor deposition (PECVD) is presented. The multi-step process consisted of pre-treatment, deposition, and post-treatment in each deposition step. We obtained low-k films with superior gap-filling properties on the trench patterns without voids or delamination. The newly developed technique for the gap-filling of submicrometer features will have a great impact on inter metal dielectric (IMD) and shallow trench isolation (STI) processes for the next generation of microelectronic devices. Moreover, this bottom up gap-fill mode is expected to be universally for other chemical vapor deposition systems.

Gap-Fill Characteristics and Film Properties of DMDMOS Fabricated by an F-CVD System

  • Lee, Woojin;Fukazawa, Atsuki;Choa, Yong-Ho
    • Korean Journal of Materials Research
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    • v.26 no.9
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    • pp.455-459
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    • 2016
  • The deposition process for the gap-filling of sub-micrometer trenches using DMDMOS, $(CH_3)_2Si(OCH_3)_2$, and $C_xH_yO_z$ by flowable chemical vapor deposition (F-CVD) is presented. We obtained low-k films that possess superior gap-filling properties on trench patterns without voids or delamination. The newly developed technique for the gap-filling of submicrometer features will have a great impact on IMD and STI for the next generation of microelectronic devices. Moreover, this bottom up gap-fill mode is expected to be universal in other chemical vapor deposition systems.

Post-Linearization of Differential CMOS Low Noise Amplifier Using Cross-Coupled FETs

  • Kim, Tae-Sung;Kim, Seong-Kyun;Park, Jin-Sung;Kim, Byung-Sung
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.4
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    • pp.283-288
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    • 2008
  • A post-linearization technique for the differrential CMOS LNA is presented. The proposed method uses an additional cross-coupled common-source FET pair to cancel out the third-order intermodulation ($IM_3$) current of the main differential amplifier. This technique is applied to enhance the linearity of CMOS LNA using $0.18-{\mu}m$ technology. The LNA achieved +10.2 dBm IIP3 with 13.7 dB gain and 1.68 dB NF at 2 GHz consuming 11.8 mA from a 1.8-V supply. It shows IIP3 improvement by 6.6 dB over the conventional cascode LNA without the linearizing circuit.

Improved Transmitter Power Efficiency using Cartesian Feedback Loop Chip

  • Chong, Young-Jun;Lee, Il-Kyoo;Oh, Seung-Hyeub
    • Journal of electromagnetic engineering and science
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    • v.2 no.2
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    • pp.93-99
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    • 2002
  • The Cartesian loop chip which is one of key devices in narrow-band Walky-Talky transmitter using RZ-SSB modulation method was designed and implemented with 0.35 Um CMOS technology. The reduced size and low cost of transmitter were available by the use of direct-conversion and Cartesian loop chip, which improved the power efficiency and linearity of transmitting path. In addition, low power operation was possible through CMOS technology. The performance test results of transmitter showed -23 dBc improvement of IMD level and -30 dEc below suppression of SSB characteristic in the operation of Cartesian loop chip (closed-loop). At that time, the transmitting power was about 37 dBm (5 W). The main parameters to improve the transmitting characteristic and to compensate the distortion in feed back loop such as DC-offset, loop gain and phase value are interfaced with notebook PC to be controlled with S/W.

Modeling of CCP plasma with H2/N2 gas (H2/N2 가스론 이용한 CCP 플라즈마 모델링)

  • Shon, Chae-Hwa
    • Proceedings of the KIEE Conference
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    • 2006.10a
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    • pp.158-159
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    • 2006
  • The resistance-capacitance (RC) delay of signals through interconnection materials becomes a big hurdle for high speed operation of semiconductors which contain multilayer interconnection layers. In order to reduce the RC delay, low-k materials will be used for inter-metal dielectric (IMD) materials. We have developed self-consistent simulation tool that includes neutral-species transport model, based on the relaxation continuum (RCT) model. We present the parametric study of the modeling results of a two-frequency capacitively coupled plasma (2f-CCP) with $N_2/H_2$ gas mixture that is known as promising one for organic low-k materials etching. We include the neutral transport model as well as plasma one in the calculation. The plasma and neutrals are calculated self-consistently by iterating the simulation of both species till a spatiotemporal steady state profile could be obtained.

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CMI Tolerant Readout IC for Two-Electrode ECG Recording (공통-모드 간섭 (CMI)에 강인한 2-전극 기반 심전도 계측 회로)

  • Sanggyun Kang;Kyeongsik Nam;Hyoungho Ko
    • Journal of Sensor Science and Technology
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    • v.32 no.6
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    • pp.432-440
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    • 2023
  • This study introduces an efficient readout circuit designed for two-electrode electrocardiogram (ECG) recording, characterized by its low-noise and low-power consumption attributes. Unlike its three-electrode counterpart, the two-electrode ECG is susceptible to common-mode interference (CMI), causing signal distortion. To counter this, the proposed circuit integrates a common-mode charge pump (CMCP) with a window comparator, allowing for a CMI tolerance of up to 20 VPP. The CMCP design prevents the activation of electrostatic discharge (ESD) diodes and becomes operational only when CMI surpasses the predetermined range set by the window comparator. This ensures power efficiency and minimizes intermodulation distortion (IMD) arising from switching noise. To maintain ECG signal accuracy, the circuit employs a chopper-stabilized instrumentation amplifier (IA) for low-noise attributes, and to achieve high input impedance, it incorporates a floating high-pass filter (HPF) and a current-feedback instrumentation amplifier (CFIA). This comprehensive design integrates various components, including a QRS peak detector and serial peripheral interface (SPI), into a single 0.18-㎛ CMOS chip occupying 0.54 mm2. Experimental evaluations showed a 0.59 µVRMS noise level within a 1-100 Hz bandwidth and a power draw of 23.83 µW at 1.8 V.

Capacitively Coupled Plasma Simulation for Low-k Materials Etching Process Using $H_2/N_2$ gas (저 유전 재료의 에칭 공정을 위한 $H_2/N_2$ 가스를 이용한 Capacitively Coupled Plasma 시뮬레이션)

  • Shon, Chae-Hwa
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.55 no.12
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    • pp.601-605
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    • 2006
  • The resistance-capacitance (RC) delay of signals through interconnection materials becomes a big hurdle for high speed operation of semiconductors which contain multi-layer interconnections in smaller scales with higher integration density. Low-k materials are applied to the inter-metal dielectric (IMD) materials in order to overcome the RC delay. Relaxation continuum (RCT) model that includes neutral-species transport model have developed to model the etching process in a capacitively coupled plasma (CCP) device. We present the parametric study of the modeling results of a two-frequency capacitively coupled plasma (2f-CCP) with $N_2/H_2$ gas mixture that is known as promising one for organic low-k materials etching. For the etching of low-k materials by $N_2/H_2$ plasma, N and H atoms have a big influence on the materials. Moreover the distributions of excited neutral species influence the plasma density and profile. We include the neutral transport model as well as plasma one in the calculation. The plasma and neutrals are calculated self-consistently by iterating the simulation of both species till a spatio-temporal steady state profile could be obtained.

A Study on Improving Efficiency of Power Amplifier using Doherty Theory for Wireless Network and Repeater (도허티 이론을 이용한 무선 네트워크 및 중계기용 전력증폭기의 효율 향상에 관한 연구)

  • Jeon Joong Sung;Choi Dong Muk
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.9 no.2
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    • pp.422-427
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    • 2005
  • In this paper, Doherty amplifier is designed by the need of improving the linearity and efficiency of wireless network and repeater for WCDMA. It is designed to maintain the high linearity and efficiency at the low efficiency period of the power amplifier after analyzing Doherty technique using the active load-pull in condition of the high efficiency power amplifier implementation according to the variation of input power. CW 1-tone experimental results at the WCDMA frequency 2.11$\~$2.17 CHz shows that Doherty amplifier, which achieves pore. add efficiency(PAE) 50$\%$ at 6dB back off the point from maximum output power 52.3dBm, obtains higher efficiency of 13.3$\%$ than class AB. finding optimum bias point after adjusted gate voltage, Doherty amplifier shows that IMD3 improves 4dB.

Digital Predistortion Algorithm using Techniques of Temperature Compensation (온도보상 기법을 적용한 디지털 방식의 사전 왜곡제거기 알고리듬)

  • Ko, Young-En;Bang, Sung-Il
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.42 no.9 s.339
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    • pp.1-10
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    • 2005
  • In this paper, we proposed predistortion algerian that can compensate temperature distortion by digital. Predistortion algorithm produces compensation value of distortion by temperature as well as system nonlinear distortion by input level, and warps beforehand signal of baseband. To prove excellency of such algorithm we applied predistortion algorithm to Saleh's high power amplifier model, and did computer simulation. As a result, P1dB increased about 0.5 dBm phase shift reduced about $0.8^{o}$ than existent the A&P PD, and predistiortion algorithm to apply temperature compensation techniques improved P1dB about 2dBm and stabilized phase shift by about $0.1^{o}$ low. When approved UMTS's sample signal to this amplifier, IMD3 of amplifier decreased 10dBm than is no temperature compensation techniques, and reduced 19dBm than signal that is no distortion.