• 전자공학회논문지 IE
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• 제43권4호
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• pp.115-121
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• 2006

본 논문에서는 통신 시스템에서 채널 전송에 의한 데이터의 오류 체크와 정정문제에 대해서 제안하였다. 제안된 LDPC 코드는 VDSL 시스템에서의 AWGN 채널 모델링에 의해 최소화된 채널 에러를 위해 사용된다. LDPC 코드는 낮은 밀도 패리티비트를 사용하기 때문에, 수학적인 복잡도가 낮고 처리 시간이 짧다. 또한 LDPC 코드의 성능은 반복 복호 알고리즘에서 긴 코드 워드에 대해 터보 코드보다 더 나은 성능을 가지고 있다. 제안된 시스템의 송신기에서 발생 행렬에 의해서 부호어가 발생되고, 수신기에서 사용된 에러 정정 알고리즘은 가중치를 갖는 Bit-flipping 방식이다. 이 방식은 기존의 Bit-flipping 방식과 달리 더 정확한 에러를 검출하고, 정정하기 위해 발생된 패리티 비트에 대해서 가중치를 주어 에러 정정을 하는 방식이다. 제안된 가중치를 갖는 Bit-flipping 알고리즘은 기존의 Bit-flipping 알고리즘에 비해서 1 dB 이상의 이득 개선을 확인할 수 있었다.

• ETRI Journal
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• 제39권3호
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• pp.319-325
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• 2017

The decoding process of a quasi-cyclic low-density parity check code requires a unique type of rotator. These rotators, called multi-size cyclic-shifters (MSCSs), rotate input data with various sizes, where the size is the amount of data to be rotated. This paper proposes a low-complexity MSCS structure for the case when the sizes have a nontrivial common divisor. By combining the strong points of two previous structures, the proposed structure achieves the smallest area. The experimental results show that the area reduction was more than 14.7% when the proposed structure was applied to IEEE 802.16e as an example.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 추계학술대회
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• pp.415-418
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• 2011

WiMAX, WLAN 등의 무선통신 시스템에 사용되는 LDPC(low-density parity check) 복호기의 핵심 기능블록인 DFU(decoding function unit)의 회로 최적화를 제안한다. 최소합(min-sum) 복호 알고리듬 기반의 DFU는 2의 보수 값과 sign-magnitude 값 사이의 변환이 필요하여 회로가 복잡해진다. 본 논문에서는 sign-magnitude 연산 기반의 DFU를 설계하여 수체계 변환과정을 제거함으로써 회로를 간소화시키고 동작속도를 향상시켰다.

• Journal of Electrical Engineering and Technology
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• 제12권3호
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• pp.1262-1270
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• 2017

Among various decoding algorithms of low-density parity-check (LDPC) codes, the min-sum (MS) algorithm and its modified algorithms are widely adopted because of their computational simplicity compared to the sum-product (SP) algorithm with slight loss of decoding performance. In the MS algorithm, the magnitude of the output message from a check node (CN) processing unit is decided by either the smallest or the next smallest input message which are denoted as min1 and min2, respectively. It has been shown that multiplying a scaling factor to the output of CN message will improve the decoding performance. Further, Zhong et al. have shown that multiplying different scaling factors (called a 2-dimensional scaling) to min1 and min2 much increases the performance of the LDPC decoder. In this paper, the simplified 2-dimensional scaled (S2DS) MS algorithm is proposed. In the proposed algorithm, we figure out a pair of the most efficient scaling factors which multiplications can be replaced with combinations of addition and shift operations. Furthermore, one scaling operation is approximated by the difference between min1 and min2. The simulation results show that S2DS achieves the error correcting performance which is close to or outperforms the SP algorithm regardless of coding rates, and its computational complexity is the lowest comparing to modified versions of MS algorithms.

• Journal of Communications and Networks
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• 제16권6호
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• pp.639-644
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• 2014

In low-density parity-check (LDPC) coded multiple-input multiple-output (MIMO) communication systems, probabilistic information are exchanged between an LDPC decoder and a MIMO detector. TheMIMO detector has to calculate probabilistic values for each bit which can be very complex. In [1], the authors presented a class of linear block codes named low-density MIMO codes (LDMC) which can reduce the complexity of MIMO detector. However, this code only supports the outer-iterations between the MIMO detector and decoder, but does not support the inner-iterations inside the LDPC decoder. In this paper, a new approach to construct LDMC codes is introduced. The new LDMC codes can be encoded efficiently at the transmitter side and support both of the inner-iterations and outer-iterations at the receiver side. Furthermore they can achieve the design rates and perform very well over MIMO channels.

• ETRI Journal
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• 제37권1호
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• pp.54-60
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• 2015

The use of serial concatenated codes is an effective technique for alleviating the error floor phenomenon of low-density parity-check (LDPC) codes. An enhanced sum-product algorithm (SPA) for LDPC codes, which is suitable for serial concatenated codes, is proposed in this paper. The proposed algorithm minimizes the number of errors by using the failed check nodes (FCNs) in LDPC decoding. Hence, the error-correcting capability of the serial concatenated code can be improved. The number of FCNs is simply obtained by the syndrome test, which is performed during the SPA. Hence, the decoding procedure of the proposed algorithm is similar to that of the conventional algorithm. The error performance of the proposed algorithm is analyzed and compared with that of the conventional algorithm. As a result, a gain of 1.4 dB can be obtained by the proposed algorithm at a bit error rate of $10^{-8}$. In addition, the error performance of the proposed algorithm with just 30 iterations is shown to be superior to that of the conventional algorithm with 100 iterations.

• 한국전자통신학회논문지
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• 제7권1호
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• pp.117-124
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• 2012

본 논문에서는 cycle-4를 쉽게 피하고 가변 부호율과 길이로 접근할 수 있게 하는 순환 치환 행렬(CPM; circulant permutation matrix)을 토대로 한 간단한 패리티 검사 행렬의 구성 방법을 제안한다. 결과적으로 부행렬 연산은 여러 CPM들의 곱셈으로 처리될 수 있으며 LDPC 부호화 계산은 매우 간단하게 수행된다. 또한 LDPC 부호의 고속 부호화 문제를 고려한다. 제안한 설계는 정규, 비정규 LDPC 부호 둘 다를 위한 간단한 행렬 연산에 근거한 고속 부호화를 가능하게 한다.

• Journal of Communications and Networks
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• 제16권5호
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• pp.479-484
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• 2014

In this paper, we consider the construction of cyclic and quasi-cyclic structured q-ary low-density parity-check (LDPC) codes over a designated small field. The construction is performed with a pre-defined sliding-window, which actually executes the regular mapping from original field to the targeted field under certain parameters. Compared to the original codes, the new constructed codes can provide better flexibility in choice of code rate, code length and size of field. The constructed codes over small fields with code length from tenths to hundreds perform well with q-ary sum-product decoding algorithm (QSPA) over the additive white Gaussian noise channel and are comparable to the improved spherepacking bound. These codes may found applications in wireless sensor networks (WSN), where the delay and energy are extremely constrained.

• 전자공학회논문지
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• 제51권10호
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• pp.72-79
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• 2014

본 논문은 PIPELINE-AWARE QC-IRA-LDPC (PA-QC-IRA-LDPC) 코드 생성 방법과 Rate-1/2 (2016,1008) PA-QC-IRA-LDPC 코드에 대한 효율적인 고속 복호기 구조를 제안한다. 제안한 방법은 비트 오류율 (BER) 성능 저하 없이 파이프라인 기법을 사용하여 임계경로를 나눌 수 있다. 또한 제안한 복호기 구조는 데이터 처리량, 하드웨어 효율 및 에너지 효율을 크게 향상시킬 수 있다. 제안한 복호기 구조는 90-nm CMOS 기술을 사용하여 합성 및 레이아웃이 수행되었으며, 이전에 보고된 복호기 구조들에 비해서 하드웨어 효율성이 53%이상 향상되었고, 훨씬 좋은 에너지 효율성을 보여준다.

• Journal of Communications and Networks
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• 제14권4호
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• pp.429-433
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• 2012

In this paper, we consider nonbinary quasi-cyclic low-density parity-check (QC-LDPC) codes and propose a method to design multiple rate codes with either fixed information bit length or block bit length, tailored to different scenarios in wireless applications. We show that the proposed codes achieve good performance over a broad range of code rates.