• Proceedings of the KIEE Conference
• /
• 2003.11c
• /
• pp.890-893
• /
• 2003

In this paper, we have designed the fractional-N frequency synthesizer for bluetooth system using 0.35-um CMOS technology and 3.3-V single power supply. The designed synthesizer consist of phase-frequency detector (PFD), charge pump, loop filter, voltage controlled oscillator (VCO), frequency divider, and sigma-delta modulator. A dead zone free PFD is used and a modified charge pump having active cascode transistors is used. A Multi-modulus prescaler having CML D flip-flop is used and VCO having a tuning range from 746 MHz to 2.632 GHz at 3.3 V power supply is used. Total power dissipation is 32 mW and phase noise is -118 dBc/Hz at 1 MHz offset.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.46 no.2
• /
• pp.72-77
• /
• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2014.10a
• /
• pp.755-758
• /
• 2014

In this paper, we propose effective Deblocking Filter hardware architecture for High Efficiency Video Coding encoder. we propose Deblocking Filter hardware architecture with less processing time, filter ordering for low area design, effective memory architecture and four-pipeline for a high performance HEVC(High Efficiency Video Coding) encoder. Proposed filter ordering can be used to reduce delay according to preprocessing. It can be used for realtime single-port SRAM read and write. it can be used in parallel processing by using two filters. Using 10 memory is effective for solving the hazard caused by a single-port SRAM. Also the proposed filter can be used in low-voltage design by using clock gating architecture in 4-pipeline. The proposed Deblocking Filter encoder architecture is designed by Verilog HDL, and implemented by 100k logic gates in TSMC $0.18{\mu}m$ process. At 150MHz, the proposed Deblocking Filter encoder can support 4K Ultra HD video encoding at 30fps, and can be operated at a maximum speed of 200MHz.

• Journal of Power Electronics
• /
• v.13 no.3
• /
• pp.369-380
• /
• 2013

Direct torque control based on space vector modulation (SVM-DTC) protects the DTC transient merits. Furthermore, it creates better quality steady-state performance in a wide speed range. The modified method of DTC using SVM improves the electrical magnitudes of asynchronous machines, such as minimizing the stator current distortions, the stator flux with electromagnetic torque without ripple, the fast response of the rotor speed, and the constant switching frequency. In this paper, the proposed method is based on two new control strategies for direct torque control with space vector modulation. First, fuzzy logic control is used instead of the PI torque and a PI flux controller to minimizing the torque error and to achieve a constant switching frequency. The voltages in the direct and quadratic reference frame ($V_d$, $V_q$) are achieved by fuzzy logic control. In this scheme, the switching capability of the inverter is fully utilized, which improves the system performance. Second, the close loop of stator flux estimation based on the voltage model and a low pass filter is used to counteract the drawbacks in the open loop of the stator flux such as the problems saturation and dc drift. The response of this new control strategy is compared with DTC-SVM. The experimental and simulation results demonstrate that the proposed control topology outperforms the conventional DTC-SVM in terms of system robustness and eliminating the bad outcome of dc-offset.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.16 no.4
• /
• pp.309-316
• /
• 2011

A PLL system has widely used for synchronizing the grid voltage at the grid-connected inverter for supplying power from the PV generation systems. In this paper, a PLL algorithm without both the loop filter and PI controller is suggested for improving the performance of synchronization at the single-phase and three-phase grid connected inverters. In order that the output voltage of a phase detector in the PLL has only a dc voltage, and it approaches to 0 when the synchronization signal is locked to the grid voltage, the feedback signals are determined by using two-phase voltages. After the PLL system with a proportional controller is modelled with the small signal analysis, the stability and steady-state error are investigated. Through the simulation studies and experimental results, the performances of the proposed PLL algorithm are verified.

• Journal of Navigation and Port Research
• /
• v.30 no.10 s.116
• /
• pp.847-853
• /
• 2006

In this paper, we designed VCO(voltage controlled oscillator} that is composed of a dielectric resonator and a varactor diode, and the PLDRO(phase locked dielectric resonator oscillator) that is combined with the sampling phase detector and loop filter. The results at 12.05 GHz show the output power is 13.54 dBm frequency tuning range approximately +/- 7.5 MHz, and power variation over the tuning range less than 0.2 dB, respectively. The phase noise which effects on bits error rate in digital communication is obtained with -114.5 dBc/Hz at 100 kHz offset from carrier, and The second harmonic suppression is less than -41.49 dBc. These measured results are found to be more improved than those of VCO without adopting PLL, and the phase noise and power variation performance characteristics show the better performances than those of conventional PLL.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.1B
• /
• pp.183-192
• /
• 2000

In this paper, the dual looped CMOS PLL with 3-250MHz input locking range at a single 13.3V is designed. This paper proposed a new PLL architecture with a current pumping algorithm to improve voltage-to-frequencylinearity of VCO(Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of75.8MHz-lGHz with a high linearity. Also, PFD(Phase frequency Detector) circuit preventing voltage fluctuation of the charge pump with loop filter circuit under the locked condition is designed. The simulation results of the PLL using 0.6 um N-well single poly triple metal CMOS technology illustrate a locking time of 3.5 us, a power dissipation of 92mW at 1GHz operating frequency with 125MHz of input frequency. Measured results show that the phase noise of VCO with V-I converter is -100.3dBc/Hz at a 100kHz offset frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.9
• /
• pp.74-80
• /
• 2009

This paper describes a $2{\sim}6GHz$ CMOS frequency synthesizer that employs only one LC-tank voltage controlled oscillator (VCO). For wide-band operation, optimized LO signal generator is used. The LC-tank VCO oscillating in $6{\sim}8GHz$ provides the required LO frequency by dividing and mixing the VCO output clocks appropriately. The frequency synthesizer is based on a fractional-N phase locked loop (PLL) employing third-order 1-1-1 MASH type sigma-delta modulator. Implemented in a $0.18{\mu}m$ CMOS technology, the frequency synthesizer occupies the area of $0.92mm^2$ with of-chip loop filter and consumes 36mW from a 1.8V supply. The PLL is completed in less than $8{\mu}s$. The phase noise is -110dBC/Hz at 1MHz offset from the carrier.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.2
• /
• pp.100-105
• /
• 2010

In this paper, a FM radio receiver integrated circuit has been developed based on $0.5{\mu}m$ CMOS process for Zero-Crossing FM demodulator over the 88MHz to 108MHz band. The receiver is designed with the low-IF architecture, and includes Low Noise Amplifier(LNA), Down-Conversion Mixer, Phase Locked Loop(PLL), IF LPF, and a comparator. The measured results of the LNA and Mixer show that the conversion gain of 23.2 dB, the input PldB of -14 dBm, and the noise figure of 15 dB. The measured analog block of the LPF and comparator show the voltage gain of over 89 dB, and the IF LPF can configure the passband from 600KHz to 1.3MHz with 100KHz step through the internal control register banks. The designed FM radio receiver operates at 4.5V with the total current consumption of 15.3mA, so the total power consumption is about 68.85mW. The commercial FM radio has been successfully received.

• Proceedings of the KIPE Conference
• /
• 2007.11a
• /
• pp.18-20
• /
• 2007

3상 계통 연계 형 인버터 시스템은 낮은 THD를 가지는 계통 전류를 공급해주기 위해 LCL 필터를 사용한다. LCL 필터를 사용하는 가장 큰 장점은 낮은 스위칭 주파수에서도 만족할 만한 수준의 THD를 가지는 계통 전류를 생성시킬 수 있다는 점이다. 반면에, 단점은 LCL필터를 포함하는 계통 연계 형 인버터 시스템의 전달함수에 하나의 공진 극점이 존재한다는 점이다. 이것은 계통 전류 제어 loop에서, 안정성 문제에 영향을 미친다. 정확한 제어를 위해서 시스템의 전달함수는 필수적이다. 여기서 중요한 점은 많은 저자들이 시뮬레이션과 실험을 할 때, 중성점이 없는 회로에서 행하지만 회로 해석을 할 때에는 중성점이 있는 회로에서 해석을 한다는 점이다. 그래서 우리는 등가 델타회로에서 LCL 필터를 포함한 전체 시스템의 수학적인 모델을 제안한다. 이 모델은 모든 인덕터와 커패시터의 기생 저항을 고려한다. 또한 이 논문은 계통 전류를 제어하기 위한 제어기의 해석적인 설계 절차를 포함한다. 제안한 수학적인 모델을 입증하기 위해, PSIM을 통한 시뮬레이션과 Simulink를 통한 시뮬레이션 결과를 비교하였다.