• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.12
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• pp.953-958
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• 2001

The antifuse is a semi-permanent memory device like a ROM which shows the open or short state, and a switch device connecting logic blocks selectively in FPGA. In addition, the antifuse has been used as a logic device to troubleshoot defective memory cells arising from SDRAM processing. In this study, we have fabricated ONO antifuses consisted of PIP structure. The antifuse shows a high resistance more than several G Ω in the normal state, and shows a low resistance less than 500 Ω after program. The program resistance variation according to temperature shows the very stable value of $\pm$20 Ω. At this time, its program voltage shows 6.7∼7.2 V and the program is performed within 1 second. Therefore this result shows that the PIP antifuse is a very stable and programmable logic device.

• Proceedings of the KSR Conference
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• 2008.06a
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• pp.417-422
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• 2008

The DC high speed circuit breaker used in Seoul Metro for line no.1.2 is Japan HITACHI and FUJI breaker, and for line no.3.4 is Whipp & Bourne MM74 breaker from UK. The years that each breakers made are 1973(line no.1), 1984(line no.3.4), So that equipments are superannuated. Nowday the for equipment exchanging is executing, equipment for exchanging were used the Secheron breaker from Swiss. but now the Intec breaker made in Korea is used. The RTU of supervisory control and data acquisition system have the capabilities that can observe, control and work the installation efficiently. In this paper, as summarizing the solving process of problem that happened the SCADA system when old-equipment exchange and concerned point for logical supervision and control of reservation factors and equipment, I'll provide the direction that can do receiving-process of control-equipment, progressed with the exchange of old-electronic equipment.

• Journal of the Korean Society for Railway
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• v.8 no.1
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• pp.1-5
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• 2005

This paper has presented the parallel cyclic redundancy check (CRC) technique that performs CRC computation in parallel superior to the conventional CRC technique that processes data bits serially. Also, it has showed that the implemented parallel CRC circuit has been successfully applied to the inductively coupled passive RFTD system working at a frequency of 13.56㎒ in order to process the detection of logical faults more fast and the system has been verified experimentally. In comparison with previous works, the proposed RFID system using the parallel CRC technique has been shown to reduce the latency and increase the data processing rates about 15％ In the results. Therefore, it seems reasonable to conclude that the parallel CRC realization in the RFID system offers a means of maintaining the integrity of data in the high speed RFID system.

• Proceedings of the KSR Conference
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• 2004.10a
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• pp.1235-1240
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• 2004

This paper has presented the parallel cyclic redundancy check (CRC) technique that performs CRC computation in parallel superior to the conventional CRC technique that processes data bits serially. Also, it has showed that the implemented parallel CRC circuit had been successfully applied to the inductively coupled passive RFID system working at a frequency of 13.56MHz in order to process the detection of logical faults more fast and the system had been verified experimentally. In comparison with previous works, the proposed RFID system using the parallel CRC technique has been shown to reduce the latency and increase the data processing rates in the results. Therefore, it seems reasonable to conclude that the parallel CRC realization in the RFID system offers a means of maintaining the integrity of data in the high speed RFID system.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.351-354
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• 2000

In the past, we proposed an IDDQ testable design method for static CMOS PLA circuits. All bridging faults can be detected in NOR planes of our testable designed PLA circuits by IDDQ testing with 4 kinds of test input vectors which are independent of the logical functions to be realized. However, the testable designed PLA circuits consume large power in the normal operation. In this paper, a new IDDQ testable design method is proposed and evaluated by some experiments. The experimental results show that the PLA circuit designed with our method can work with low power consumption than the previous one.

• Journal of Korean Institute of Industrial Engineers
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• v.17 no.2
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• pp.63-74
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• 1991

An expert scheduling system on real time basis for computer-aided manufacturing systems has been developed. In developing expert scheduling system, the most time-consuming job is to obtain rules from expert schedulers. An efficient process of obtaining rules directly form the schedules produced by expert schedulers is proposed. By the process, a set of complete and minimal set of rules is obtained. During a real time scheduling, when given information on possible values of elements, the rules produce possible values of decision elements, where logical explanations of the result may be offered in terms of chaining rules. The learning and scheduling processes have been simulated with an automated manufacturing line engaged in the production of circuit boards.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2296-2298
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• 1998

In this paper, an on-chip learning pulse-mode digital neural network with a massively parallel yet compact and flexible network architecture is suggested. Algebraic neural operations are replaced by stochastic processes using pseudo-random sequences and simple logic gates are used as basic computing elements. Using Back-propagation algorithm both feed-forward and learning phases are efficiently implemented with simple logical gates. RNG architecture using LFSR and barrel shifter are adopted to avoid some correlation between pulse trains. Suggested network is designed in digital circuit and its performance is verified by computer simulation.

• Journal of Power Electronics
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• v.16 no.1
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• pp.133-141
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• 2016

This paper focuses on the development of a Five-Level Flying-Capacitor Dual Buck Inverter (FLFCDBI) based on the main circuit of dual buck inverters. This topology has been described as not having any shoot-through problems, no body-diode reverse recovery problems and the half-cycle work mode found in the traditional Multi-Level Flying-Capacitor Inverter (MLFCI). It has been shown that the flying-capacitor voltages of this inverter can be regulated by the redundant state selection within one pole. The voltage balance of the flying-capacitors can be achieved by charging or discharging in the positive (negative) half cycles by choosing the proper logical algorithms. This system has a simple structure but demonstrates improved performance and reliability. The validity of this inverter is conformed through computer-aided simulation and experimental investigations.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.3 no.1
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• pp.18-30
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• 1985

This paper describes a logical design of ternary arithmetic circuits based on T-gates. A new circuit of T-gate is proposed which is improved in the stability of operation, and a ternary adder, subtracter, multiplier and divider using the T-gates are realized. The realization of the circuits is based on the Mod-3, system and the Signed Ternary system using digit 0, 1, 2 and -1, 0, +1 as arithmetic states.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.686-689
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• 2014

This Paper is about the study that use the IPM(Intelligent Power Module) which is a integrated switching module to drive inverter gates for driving of a multi-pole BLDC(Brushless Direct Current) motors. When designing a inverter using the various manufacturers IPM, it suggests a electronic circuit system to evaluate the electrical and logical characteristics of the IPM with various brands.