• The KIPS Transactions:PartA
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• v.17A no.1
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• pp.27-32
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• 2010

Logical Effort is a simple hand-calculated method that measures quick delay estimation. It has the advantage of reducing the design cycle time. However, it has shortcomings in designing a path for minimum area or power under a fixed-delay constraint. In this paper, we propose an equal delay model and, based on this, a method of optimizing power-delay efficiency in a logical path. We simulate three designs of an eight-input AND gate using our technique. Our results show about 40% greater efficiency in power dissipation than those of Logical Effort method.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.3
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• pp.103-110
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• 2013

Logical Effort [1, 2] is a simple hand-calculated method that measures quick delay estimation. It has the advantage of reducing the design cycle time. However, it has shortcomings in designing a path for minimum area or power under a fixed-delay constraint. The method of overcoming the shortcomings is shown in [3], but it is constrained for a single logical path. This paper presents an advanced gate sizing method in multiple logical paths based on the equal delay model. According to the results of the simulation, the power dissipation for both the existing logical effort method and proposed method is almost equal. However, compared with the existing logical effort method, it is about 52 (%) more efficient in space.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.37-44
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• 2005

In this paper, a new type of the TC-to-BC encoder for high speed flash ADC's, called the Successive Selection Encoder (SSE), is proposed. In contrast to the conventional fat tree encoder based on OR operations, the W- outputs, in the new design, are obtained directly from TC inputs through simple MUX operations. The detailed structure of the SSE has been determined systematically by the method of the logical effort and the simulation oil Hynix 0.25um process. The theoretical and experimental results show that (1) it is not required to generate one-out-of-n signals, (2) the number of gates is reduced by the factor of 1/3, and (3) the speed is improved more than 2-times, compared to the fat tree encoder. It is speculated that the SSE proposed in this study is an effective solution for bottleneck problems in high speed ADCs.

• The Journal of Korean Association of Computer Education
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• v.9 no.3
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• pp.85-96
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• 2006

This study analyzes a phenomenon observed in the problem-solving process using ICT that field learners prioritize functional and logical fields. The purpose of this study is to anticipate the future direction of education utilizing ICT and to explore what effort is needed to increase balanced ability of utilizing ICT in the area of education. To analyze the patterns of ICT usage in education, students were asked to solve the problems including functional and logical requests by using the program of framing document. That results were marked in accordance with standards framed in both functional and logical fields. As a result, students utilized the ICT functional field more than logical one. Therefore, we confirm learning through ICT is more effective on functional sides than on logical sides. We also confirm the excellency of ICT's functional sides in such variables as major, grade, computer capability and qualification, etc.

• Journal of the Korean Society for information Management
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• v.12 no.2
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• pp.85-101
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• 1995

Conventional indexing sytstems support only full-text indexing method for electronic documents and do not use logical structure of documents in retrieval. Most electronic documents are in different formats depending on various systems. Also, they only indicate physical style of the document without considering any logical structure. Thus, in the effort to standardize the exchange of documents. IS0 developed SGML(Stadard Generalized Markup Language) which contains information about logical structure of the documents. In this paper, to resolve the disadvantages of full-text indexing method and to use standard document format. indexing system for SGML document is designed and implemented. In this system, user can assign indexing domain on elements, thus the logical structure of document is reflected in retrieving information. Various retrieval methods can be implemented by using the structural information of the document. In addition, automatic indexing for SGML Hangul document is supported in this system

• Journal of KIBIM
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• v.12 no.3
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• pp.30-38
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• 2022

Railway is compsed in various components, such as subgrade, track bed, sleeper, rail, and overhead line, on a linear space. Therefore, comprehensive work for various design standards and guidelines is required when designing a railway facility. For this reason, much time and effort are required to review the relevant design standards and guidelines. While, automatic legal check system for BIM models has been developed in the architectural engineering, it has not been developed in the railway engineering. This study reviews the korean design standard and the korean code for railway engineering, and suggests some rule items of logical information. Comparing the suggested rule items to the railway BIM library, items of logical information and additional attribute information are obtained. The analysis results of railway design standards and BIM library presented in this study would be utilized for defining rule-set items that is essential for development of the automatic legal check system for railway BIM models.

• Journal of KIISE:Information Networking
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• v.31 no.2
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• pp.224-232
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• 2004

To guarantee the reliability in multicast transmission, researches providing reliability through hierarchical control tree which is independent on data channel tree are known to provide high scalability. However, the logical control tree in transport layer constructed without topology information of the corresponding network layer tree may inefficiently use the network resources because the logical control tree is not closely related to the tree topology of the network layer. A router assisted control tree mechanism presented in this paper would improve the efficiency of the link as well as it would remove the replicated data. In addition, it requires to a router a small change which examines the message type of the control tree.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10a
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• pp.87-90
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• 1996

Inherently safe plants are maintained through the systematic identification of potential hazards, and various hazard evaluation methods have been developed. Recently, much effort is given into the development of automated hazard evaluation system by introducing the expert system. An automated system will help to obtain consistency and to make the result more reliable. HAZOP study is one of the most systematic and logical evaluation procedure. However, it has disadvantages: experts should participate at the same time, the detailed study requires much man-hour, and the results depend on the expertise of the experts. Therefore, the automation of hazard evaluation is necessary to reduce the required time and to get the consistent evaluation results. In this study, HAxSYM, an expert system to automate HAZOP study, is developed. The case studies are performed to validate the effectiveness of the developed system, and the results are compared to the results of traditional method.

• Korean Institute of Interior Design Journal
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• no.25
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• pp.272-279
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• 2000

It can be characterized that contemporary architects intend to establish architectonics which can make it possible to reinterpret the attribute of movement in space and its programming differed from the traditional perception in moving in and out any space through disjoining and reorganizing human behavior and event. This intends reflect new paradigm for subjugating the compelled fuctioning of modern Architecture. This Study review those intends focused on programming as a pre-disign schema. In those intends, it connotes the effort of establishing more systemic and logical approach through deconstruction and disprogramming the existing from, space, elements and human on the basis of his own schematic conception as substitution of function in modern architecture.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.767-772
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• 2005

The Internet is a packet switched network which offers best-effort service, but current IP network provide enhanced services such Quality of Services, Virtual Private Network (VPN) services, Distribute Firewall and IP Security Gateways. All such services need packet classification for determining the flow. The problem is performing scalable packet classification at wire speeds even as rule databases increase in size. Therefore, this research offer packet classification algorithm that increase classifier performance when working with enlarge rules database by rearrange rule structure into Bitmap Intersection Lookup (BIL) tables. It will use packet's header field for looking up BIL tables and take the result with intersection operation by logical AND. This approach will use simple algorithm and rule structure, it make classifier have high search speed and fast updates.