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Design of the Successive Selection Encoder by the Logical Effort for High Flash Speed ADC's  

Lee Kijun (Division of Electrical and Computer Engineering, Chungnam Nat'l University)
Choi Kyusun (Dept. of Computer Science and Angineering, Pennsylvania State University)
Kim Byung-soo (Samsung Electronics)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.42, no.4, 2005 , pp. 37-44 More about this Journal
Abstract
In this paper, a new type of the TC-to-BC encoder for high speed flash ADC's, called the Successive Selection Encoder (SSE), is proposed. In contrast to the conventional fat tree encoder based on OR operations, the W- outputs, in the new design, are obtained directly from TC inputs through simple MUX operations. The detailed structure of the SSE has been determined systematically by the method of the logical effort and the simulation oil Hynix 0.25um process. The theoretical and experimental results show that (1) it is not required to generate one-out-of-n signals, (2) the number of gates is reduced by the factor of 1/3, and (3) the speed is improved more than 2-times, compared to the fat tree encoder. It is speculated that the SSE proposed in this study is an effective solution for bottleneck problems in high speed ADCs.
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Times Cited By KSCI : 1  (Citation Analysis)
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