• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.12a
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• pp.209-212
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• 2000

This paper describes the design and implementation of a hard- wired AGV controller using CPLD(Complex Programmable Logic Device). The proposed controller manages a guidance equipment, motor and I/O sequence controller for a self-control traveling. Compared with a conventional $\mu$-processor, the CPLD controller using a hard-wired control method can reduce a difficult programming process. Also, the total costs of production are reduced, such as development time, product's size and difficulty because memory, combinational logic and sequential logics are implemented by CPLD. The Controller designed using behavioral description method with VHDL and was synthesized by MAX＋Plus II of the ALTERA co. We implemented controller using EPF10K10LC84-4 device.

• Nuclear Engineering and Technology
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• v.54 no.1
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• pp.310-317
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• 2022

The mass attenuation coefficient is the primary physical parameter to model narrow beam gamma-ray attenuation. A new machine learning based approach is proposed to model gamma-ray shielding behavior of composites alternative to theoretical calculations. Two fuzzy logic algorithms and a neural network algorithm were trained and tested with different mixture ratios of vanadium slag/epoxy resin/antimony in the 0.05 MeV-2 MeV energy range. Two of the algorithms showed excellent agreement with testing data after optimizing adjustable parameters, with root mean squared error (RMSE) values down to 0.0001. Those results are remarkable because mass attenuation coefficients are often presented with four significant figures. Different training data sizes were tried to determine the least number of data points required to train sufficient models. Data set size more than 1000 is seen to be required to model in above 0.05 MeV energy. Below this energy, more data points with finer energy resolution might be required. Neuro-fuzzy models were three times faster to train than neural network models, while neural network models depicted low RMSE. Fuzzy logic algorithms are overlooked in complex function approximation, yet grid partitioned fuzzy algorithms showed excellent calculation efficiency and good convergence in predicting mass attenuation coefficient.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.5B no.3
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• pp.277-282
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• 2005

This paper describes a step-down AC voltage regulator using an AC chopper and auxiliary transformer, which is a series connected to the main input. The detail design of the AC regulator, logic and PWM pattern of the AC chopper is described and the three-phase AC regulator using two single­phase AC choppers with a three transformer configuration is proposed for three-phase application. The proposed three-phase system has the advantages of lower system cost due to reduced switch number and gate driver circuit as well as advantages of decreased size and weight because it uses a series compensated scheme. The proposed AC regulator has many benefits such as fast voltage control, high efficiency and simple control logic. Experimental results indicate that it can be used as a step-down AC voltage regulator for power saving purposes very efficiently.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.11
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• pp.56-64
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• 1992

The sum-of-product type MVL (Multiple-valued logic) functions can be directly transformed into the exclusive-sum-of-literal-product(ESOLP) type MVL functions with a substitution of the OR operator with the exclusive-OR(XOR) operator. This paper presents an algorithm that can reduce the number of minterms for the purpose of minimizing the hardware size and the complexity of the circuit in the realization of ESOLP-type MVL functions. In Boolean algebra, the joinable true minterms can form the cube, and if some cubes form a cube-chain with adjacent cubes by the insertion of false cubes(or, false minterms), then the created cube-chain can become a large cube which includes previous cubes. As a result of the cube grouping, the number of minterms can be reduced artificially. Since ESOLP-type MVL functions take the MIN/XOR structure, a XOR circuit and a four-valued MIN/XOR dynamic-CMOS PLA circuit is designed for the realization of the minimized functions, and PSPICE simulation results have been also presented for the validation of the proposed algorithm.

• Proceedings of the KIPE Conference
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• 2009.11a
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• pp.135-138
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• 2009

In this paper, a novel maximum power point tracking (MPPT) for a PMSG-based variable speed wind power system is proposed using the fuzzy logic algorithm. The control algorithm is developed based on the normal hill climb searching (HCS) method, commonly used in wind energy conversion systems (WECS). The inputs of fuzzy-based controller are the derivations of DC output power and the step size of DC/DC converter duty cycles. The main advantages of the proposed MPPT method are no need to measure the wind velocity and the generator rotational speed. As such, the control algorithm is independent of turbine characteristics, achieving the fast dynamic responses with non-linear fuzzy systems. The effectiveness of the proposed MPPT strategy has been verified through the simulated results.

• Journal of KIISE:Software and Applications
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• v.31 no.11
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• pp.1560-1567
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• 2004

In temporal logic model checking, the number of states is exponentially increased by the size of a model. This is called the state explosion problem. Abstraction, partial order, symmetric, etc. are widely used to avoid the problem. They reduce a number of states by exploiting structural information in a model. Instead, this paper proposes the relay model checking that decomposes a temporal formula to be verified into several sub-formulas and then model checking them one by one. As a result, we solve complex games that can't handle with previous techniques.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.215-220
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• 2007

Leakage current of CMOS circuits has become a major factor in VLSI design these days. Although many circuit-level techniques have been developed, most of them require significant amount of designers' effort and are not aligned well with traditional VLSI design process. In this paper, we focus on technology mapping, which is one of the steps of logic synthesis when gates are selected from a particular library to implement a circuit. We take a radical approach to push the limit of technology mapping in its capability of suppressing leakage current: we use a probabilistic leakage (together with delay) as a cost function that drives the mapping; we consider pin reordering as one of options in the mapping; we increase the library size by employing gates with larger gate length; we employ a new flipflop that is specifically designed for low-leakage through selective increase of gate length. When all techniques are applied to several benchmark circuits, leakage saving of 46% on average is achieved with 45-nm predictive model, compared to the conventional technology mapping.

• Journal of Information Display
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• v.6 no.4
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• pp.11-15
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• 2005

We propose a current mode logic circuit design method for LTPS TFT for enhancing circuit operating speed. Current mode inverter/buffers with passive resistive load had been designed and fabricated. Measurement results indicated that the smaller logic swing of the current mode allowed significantly faster operation than the static CMOS. In order to reduce the chip size, both all pTFT and all nTFT active load current mode inverter/buffer had been designed and analyzed by HSPICE simulation. Even though the active load current mode circuits were inferior to the passive load circuits, it was superior to static CMOS gates.

• Progress in Superconductivity and Cryogenics
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• v.8 no.2
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• pp.17-19
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• 2006

A novel clock distribution technique for pipelined-RSFQ logics using variable Bias Currents of JTLs as delay-medium is newly proposed. RSFQ logics consist of several logic gates or blocks connected in a pipeline structure. And each block has variable delay difference. In the structure, this clock distribution method generates a set of clock signals for each logic blocks with suitable corresponding delays. These delays, in the order of few to tens of pS, can be adjusted through controlling bias current of JTL of delay medium. While delays with resistor value and JJ size are fixed at fabrication stage, delay through bias current can be controlled externally, and thus, is heavily investigated for its range as well as correct operation within current margin. Possible ways of a standard delay library with modular structure are sought for further modularizing Pipelined-RSFQ applications. Simulations and verifications are done through WRSpice with Hypres 3-um process parameters.

• Journal of the Korean Institute of Intelligent Systems
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• v.12 no.2
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• pp.135-143
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• 2002

In this study, Multi-Values Logic processor was designed using the basic circuit of the electric current mode CMOS. First of all, binary FFT(Fast courier Transform) was extended and high-speed Multi-Valued Logic processor was constructed using a multi valued logic circuit. Compared with the existing two-valued FFT, the FFT operation can reduce the number of transistors significantly and show the simplicity of the circuit. Moreover, for the construction of amount was used inside the FFT circuit with the set of redundant numbers like {0, 1, 2, 3}. As a result, the defects in lines were reduced and it turned out to be effective in the aspect of normality an regularity when it was used designing VLSI(Very Large Scale Integration). To multiply FFT, the time and size of the operation was used toed as LUT(Lood Up Table).