• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1071-1073
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• 2000

The use of HDL(Hardware Description Language) is now central to the ASIC(Application Specific Integrated Circuit). HDL-based ASIC can simplify the process of development and has a competition in market because it reduce the consuming time for the design of IC(Integrated circuit) in system level. Therefore, the development of power electronics system on chip (SOC), to design microcontroller and switching logic as one chip, is required extremely for the purpose of having reliability and low cost in power electronics which is based on switching elements. The major application of SOC is variable converter, active filter inverter for induction motor. UPS and power supply with a view to reducing electro-magnetic pollution.

• Proceedings of the KIEE Conference
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• 2001.10a
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• pp.36-38
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• 2001

A neutron controls a nuclear fission in the core of a reactor. Drive system for in-core neutron detector is an equipment that drives the detector and cable to survey neutron flux in the reactor. The drive system introduced by this paper was designed for mock-up system and fabricated to drive two drivers that having a different function. The system consists of a driver assembly, a power transmission part, and cable storage part. And there is a control panel that contains PLC and inverter. This paper is going to introduce the design and certify the operation status of completed system by control panal. And we conducted the test for torque measurement.

• Fire Science and Engineering
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• v.10 no.2
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• pp.28-39
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• 1996

A recently developed electro-thermal simulation methodology is used to analyze the behavior of a PWM(Pulse-Width-Modulated) voltage source inverter which uses IGBT(Insulated Gate Bipolar Transistor) as the switching devices. In the electro-thermal network simulation methdology, the simulator solves for the temperature distribution within the power semiconductor devices(IGBT electro-thermal model), control logic circuitry, the IGBT gate drivers, the thermal network component models for the power silicon chips, package, and heat sinks as well as the current and voltage within the electrical network. The thermal network describes the flow of heat form the chip surface through the package and heat sink and thus determines the evolution of the chip surface temperature used by the power semiconductor device models. The thermal component model for the device silicon chip, packages, and heat sink are developed by discretizing the nonlinear heat diffusion equation and are represented in component from so that the thermal component models for various package and heat sink can be readily connected to on another to form the thermal network.

• International Journal of Air-Conditioning and Refrigeration
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• v.15 no.2
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• pp.54-60
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• 2007

In this paper, we suggest the high efficient control method based on general PI control law for a variable speed refrigeration system. In the variable speed refrigeration system, the capacity and the superheat are mainly controlled by an inverter and an electronic expansion valve, respectively, for saving energy and improving coefficient of performance. Thus, we proposed a decoupling model to eliminate the interfering loop between the capacity and superheat at first. Next, we designed PI controller to control the capacity and superheat independently and simultaneously. Finally, the control performance was investigated through some experiments. The experimental results showed that the proposed PI controller based on the decoupling model can obtain good control performance under the various control references and thermal load.

• Journal of Sensor Science and Technology
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• v.28 no.1
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• pp.17-22
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• 2019

As CMOS technology scales down, reliability is becoming an important concern for VLSI designers. This paper analyzes gate-oxide breakdowns (i.e., the time-dependent dielectric-breakdown (TDDB) aging effect) as a reliability issue for combinational circuits with 45-nm technology. This paper shows simulation results for the noise margin, delay, and power using a single inverter-chain circuit, as well as the International Symposium on Circuits and Systems (ISCAS)'85 benchmark circuits. The delay and power variations in the presence of TDDB are also discussed in the paper. Finally, we propose a novel method to compensate for the logic failure due to dielectric breakdowns: We used a higher supply voltage and a negative ground voltage for the circuit. The proposed method was verified using the ISCAS'85 benchmark circuits.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.2
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• pp.254-259
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• 1987

This paper describes the CMOS standard cell library implemented in double metal single poly gate process with 3\ulcornerm design rule, and its results of testing. This standard cell library contains total 33 cells of random logic gates, flip-flop gates and input/output buffers. All of cell was made to have the equal height of 98\ulcornerm, and width in multiple constant grid of 9 \ulcornerm. For cell data base, the electric characteristics of each cell is investigated and delay is characterized in terms of fanout. As the testing results of Ring Oscillator among the cell library, the average delay time for Inverter is 1.05 (ns), and the delay time due to channel routing metal is 0.65(ps)per unit length.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.91-105
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• 2016

Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. It is revealed that hetero - material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of ${\Phi}_{M1}/{\Phi}_{M2}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.

• Journal of IKEEE
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• v.11 no.4
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• pp.129-136
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• 2007

In this paper, a simple but effective Dataline Redundancy Circuit (DRC) is proposed for a dual-port 1T-SRAM embedded in Display ICs. The DRC designed in the dual-port $320{\times}120{\times}18$-bit 1T-SRAM is verified in a 0.18-um CMOS 1T-SRAM process. In the DRC, because its control logic circuit can be implemented by a simple Shift Logic Circuit (SLC) with only an inverter and a NAND that is much simpler than the conventional, it can be placed in a pitch as narrow as a bit line pair. Moreover, an improved version of the SLC is also proposed to reduce its worst-case delay from 12.3ns to 5.9ns by 52%. By doing so, the timing overhead of the DRC can be hidden under the row cycle time because switching of the datalines can be done between the times of the word line setup and the sense amplifier setup. The area overhead of the DRC is estimated about 7.6% in this paper.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.7
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• pp.493-502
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• 2001

This paper propose a new built-in current sensor(BICS) for current testing that has some advantages compared with conventional logic testing. The designed BICS detects the fault in circuit under test (CUT) and makes a Pass/Fail signal by comparison between CUT current and duplicated inverter current. The proposed circuit consists of a differential amplifier, a comparator and a inverter. It requires 10 MOSFETs and 3 inverters. Since the designed BICS do not require the extra clock, the added extra pin is only one output pin. The mode selection is not used in this circuit. Therefore we can apply the circuit to on-line testing. The validity and effectiveness are verified through the HSPICE simulation of circuits with defects. When CUT is a 8$\times$8 parallel multiplier, area overhead of the BICS is about 4.34%.

• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.1
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• pp.55-64
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• 2002

Due to the friction characteristics of cylinders and the rail of a passenger car, in the system actuated with hydraulic systems, there exist dead zones, which can not be controlled by a PID controller. In this paper, the friction characteristics of a cylinder is examined, which may cause the abrupt increase of the acceleration in the zero-crossing speed region. To overcome the drawbacks of a PID controlled hydraulic system, a zooming fuzzy logic controller is designed and finally an improved hybrid controller is Proposed. The proposed controller is composed of the PID controller and the zooming fuzzy controller. The effectiveness of the proposed control scheme is shown by simulation and experimental results, In which the proposed hybrid control method yields good control performance not only in the zero-crossing speed region but also In the overall control region including steady-state region.