• Journal of Engineering Education Research
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• v.2 no.1
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• pp.10-16
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• 1999

In this paper, we developed the internet-based educational software package (DVLab) for design and virtual experiment of the digital logic circuits. The DVLab consists of the LogicSim module for design and simulation of digital combinational/sequantial logic circuits, micro-controller application circuits and the BreadBoard module for virtual experiment and the Theory module for lecture and the Report/ReportChecker module and some other utility modules. All developed modules can be run as application programs as well as applets in the Internet. The LogicSim and the BreadBoard support real time clock function, output verification function on the designed circuits, trace function of logic values, copy-protection function of designed circuits and provide various devices including logic gates, TTLs, LED, buzzer, and micro-controller. The educational model of digital logic circuit design and experiment using the DVLab is also presented in this paper.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.359-362
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• 2010

In this study, inverter logic circuits on a plastic substrate are built with two top-gate FETs in series on a single ZnO nanowire. The voltage transfer characteristics of the ZnO nanowire-based inverter logic circuit exhibit a clear inverting operation. The logic swing, gain and transition width of the inverter logic circuit is about 90 %, 1.03 and 1.2 V, respectively. The result of mechanical bending cycles of the inverter logic circuit on a plastic substrate shows that the stable performance is maintained even after many hundreds of bending cycles.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.3
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• pp.613-623
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• 2011

In this paper, we present a method on the construction of quinternary logic circuits using Perfect shuffle. First, we discussed the input-output interconnection of quinternary logic function using Perfect Shuffle techniques and Kronecker product, and designed the basic cells of performing the transform matrix and the reverse transform matrix of quinternary Reed-Muller expansions(QRME) using addition circuit and multiplication circuit of GF(5). Using these basic cells and the input-output interconnection technique based on Perfect Shuffle and Kronecker product, we implemented the quinternary logic circuit based on QRME. The proposed design method of QRME is simple and very efficient to reduce addition circuits and multiplication circuits as compared with other methods for same logic function because of using matrix transform based on modular structures. The proposed design method of quinternary logic circuits is simple and regular for wire routing and possess the properties of concurrency and modularity of array.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.1
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• pp.59-64
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• 2008

In this paper, we developed an virtual lecture to study digital logic circuits. The contents is intended fer the students without or with little knowledge about electrics or electronics. For the beginners, the lecture contains the basic electronics and basic circuit theory as well as the degital logic circuits to be more practical lecture. And we developed the virtual circuit lab which uses real-like devices, circuits and interactive objects for the students to experience practical digital circuits. With the features described above, this contents would be useful for the beginners who want to studying digital logic circuits.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.1
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• pp.32-40
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• 1999

The analysis of logic function is performed by the spectral coefficients which transform the function domain data into the spectral domain data. By using the spectral techniques, analysis of MVL circuits is performaed, and the fault analysis and detecting methods of multiple-valued logic circuits are proposed in this paper.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.82-82
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• 2008

One-dimensional (1D) nanowires have been received much attention due to their potential for applications in various field. Recently some logic applications fabricated on various nanowires, such as ZnO, CdS, Si, are reported. These logic circuits, which consist of two- or three field effect transistors(FETs), are basic components of computation machine such as central process unit (CPU). FETs fabricated on nanowire generally have surrounded shapes of gate structure, which improve the device performance. Highly integrated circuits can also be achieved by fabricating on nano-scaled nanowires. But the numerical and SPICE simulation about the logic circuitry have never been reported and analyses of detailed parameters related to performance, such as channel doping, gate shapes, souce/drain contact and etc., were strongly needed. In our study, NAND and NOT logic circuits were simulated and characterized using 2- and 3-dimensional numerical simulation (SILVACO ATLAS) and built-in spice module(mixed mode).

• Journal of Engineering Education Research
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• v.6 no.1
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• pp.5-14
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• 2003

This paper presents a simplified web-based simulator for digital logic circuits with which several important principles related to digital logic circuits can be understood and confirmed. The proposed simulator is implemented to have several simplified functions which are essential to the learning process of digital logic circuits. The learners by themselves simulate several digital logic circuits on the web under specific input conditions and the design/analysis of digital logic circuits can be available. The proposed simulator, combined with multimedia contents, can be used as an auxiliary educational tool and enhance the improved learning efficiency. The results of this paper can be widely used to improve the efficiency of web-based educations in the cyber space. Several simulation results are illustrated as examples to show the validity of the proposed web-based simulator.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.33 no.2
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• pp.47-55
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• 1984

This paper is concerned with a computer-aided state assignment, that is, coding race-free internal states of asynchronous sequential circuits, and a method for minimizing the combinational network of asynchronous sequential circuits. The FORTRAN version of the peoposed algorithm results in race-free state assignments and reduction of the number of connections and gates with near minimal hardware cost. Some examples are designed by the proposed computer program to illustrate the algorithm in this paper. Finally, results are compared with those of the other methods.

• Progress in Superconductivity
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• v.9 no.2
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• pp.157-161
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• 2008

Due to high speed operations and ultra low power consumptions RSFQ logic circuit is a very good candidate for future electronic device. The focus of the RSFQ circuit development has been on the advancement of analog-to-digital converters and microprocessors. Recent works on RSFQ ALU development showed the successful operation of an 1-bit block of ALU at 40 GHz. Recently, the study of an RSFQ analog-to-digital converter has been extended to the development of a single chip RF digital receiver. Compared to the voltage logic circuits, RSFQ circuits operate based on the pulse logic. This naturally leads the circuit structure of RSFQ circuit to be pipelined. Delay time on each pipelined stage determines the ultimate operating speed of the circuit. In simulations, a two junction Josephson transmission line's delay time was about 10 ps, a splitter's 14.5 ps, a switch's 13 ps, a half adder's 67 ps. Optimization of the 4-bit ALU circuit has been made with delay time consideration to operate comfortably at 10 GHz or above.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.43-53
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• 1997

In this paper, the optimal synthesis algorithm of multiple-valued logic circuits using universal logic modules (ULM) U$_{f}$ based on 3-variable ternary reed-muller expansions is presented. We check the degree of each varable for the coefficients of reed-muller expansions and determine the order of optimal control input variables that minimize the number of ULM U$_{f}$ modules. The order of optimal control input variables is utilized the realization of multiple-valued logic circuits to be constructed by ULM U$_{f}$ modules based on reed-muller expansions using the circuit cost matrix. This algorithm is performed only unit time in order to search for the optimal control input variables. Also, this algorithm is able to be programmed by computer and the run time on programming is O(p$^{n}$ ).