• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.281-284
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• 2001

This paper describes an analog multi-phase delay-locked loop (DLL) to solve the harmonic lock problem using current-starved inverter and shunt-capacitor delay cell. The DLL can be used not only as an internal clock buffer of microprocessors and memory It's but also as a multi-phase clock generator for gigabit serial interfaces. The proposed circuit was simulated in a 0.25${\mu}{\textrm}{m}$ CMOS technology to solve harmonic lock problem and to realize fast lock-on time and low-jitter we verified time interval less than 40 ps as the simulation results.

• Journal of Advanced Marine Engineering and Technology
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• v.25 no.6
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• pp.1353-1361
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• 2001

Vortex lock-on or resonance behind a circular cylinder is visualized using a time-resolved PW when a single frequency oscillation is superimposed on the mean incident velocity. For vector processing, a cross-correlation algorithm in conjunction with a recursive correlation and interrogation window shifting techniques is used. Measurements are made of the Karmas and streamwise vertices in the wake-transition regime at Reynolds lumber 360. When lock-on occurs, the vortex shedding frequency is found to be half the oscillation frequency as expected from previous experiments. At the lock-on state, the Karman vortices are observed to be more disordered by the increased strength and spanwise wavelength of the streamwiee vortices, which lead? to a strong three-dimensional motion.

• Journal of computational fluids engineering
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• v.6 no.4
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• pp.26-34
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• 2001

The flow past a circular cylinder forced to vibrate transversely is numerically simulated by solving the two-dimensional Navier-Stokes equations modified by the vibration velocity of a circular cylinder at a Reynolds number of 164. The higher-order finite difference scheme is employed for the spatial discretization along with the second order Adams-Bashforth and the first order backward-Euler time integration. The calculated cylinder vibration frequency is between 0.60 and 1.30 times of the natural vortex-shedding frequency. The calculated oscillation amplitude extends to 25% of the cylinder diameter and in the case of the lock-in region it is 60%. It is made clear that the cylinder oscillation has influence on the wake pattern, the time histories of the drag and lift forces, power spectral density and phase diagrams, etc. It is found that these results include both the periodic (lock-in) and the quasi-periodic (non-lock-in) state. The vortex shedding frequency equals the driving frequency in the lock-in region but is independent in the non-lock-in region. The mean drag and the maximum lift coefficient increase with the increase of the forcing amplitude in the lock-in state. The lock-in boundaries are also established from the present direct numerical simulation.

• 한국전산유체공학회:학술대회논문집
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• 2001.05a
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• pp.181-188
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• 2001

The flow past a circular cylinder forced to vibrate transversely is numerically simulated by solving the two-dimensional Wavier-Stokes equations modified by the vibration velocity of a circular cylinder at a Reynolds number of 164. The higher-order finite difference scheme is employed for the spatial discretization along with the second order Adams-Bashforth and the first order backward-Euler time integration. The calculated cylinder vibration frequency is between 0.60 and 1.30 times of the natural vortex-shedding frequency. The calculated oscillation amplitude extends to $25\%$ of the cylinder diameter and in the case of the lock-in region it is $60\%$. It is made clear that the cylinder oscillation has influence on the wake pattern, the time histories of the drag and lift forces, power spectral density and phase diagrams, etc. It is found that these results include both the periodic (lock-in) and the quasi-periodic (non-lock-in) state. The vortex shedding frequency equals the driving frequency in the lock-in region but is independent in the non-lock-in region. The mean drag and the maximum lift coefficient increase with the increase of the forcing amplitude in the lock-in state. The lock-in boundaries are also established from the present direct numerical simulation.

• 한국가시화정보학회:학술대회논문집
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• 2001.12a
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• pp.86-99
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• 2001

Vortex lock-on or resonance in the flow behind a circular cylinder is investigated from a time-resolved PIV when a single frequency oscillation is superimposed on the mean incident velocity. Measurements are made of the $K\acute{a}rm\acute{a}n$ and streamwise vortices in the wake-transition regime at the Reynolds number 360. Streamwise vortices at the lock-on and natural shedding states are observed, as well as the changes in the wake region with the change of the shedding frequency of lock-on state. When lock-on occurs, the vortex shedding frequency is found to be half the oscillation frequency as expected from previous experiments. At the lock-on state, the $K\acute{a}rm\acute{a}n$ vortices are observed to be more disordered by the increased strength and spanwise wavelength of the streamwise vortices, which leads to a strong three-dimensional motion. Recirculation and vortex formation region at the lock-on state is reduced as the oscillating frequency is increased. By comparing the Reynolds stresses at the lock-on and natural shedding states, $\bar{u'u'}\;and \;\bar{u'u'}$ at the lock-on state are concentrated on the shear layer around the cylinder. The $\bar{u'u'}\;at\;f_o/f_n=2.0$ has a large value near the centerline, compared with that of other cases. Considering the traces of maximum of u', in the wake region near the cylinder, wake width at the lock-on state is wider than that at the natural shedding state.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1836-1840
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• 2003

This paper, we propose a new phase-locked loop (PLL) system with the controllable output phase, independent from the output frequency, and lock-up time. This PLL system has a dual control loop is described, the inner loop greatly improved VCO characteristic such as faster speed response as well as higher operation bandwidth, to minimize the effect of the VCO noise and the power supply variation and also get better linearity of VCO output. The main loop is the heart of this PLL which greatly improved the output frequency instability due to the external high frequency noise coupling to the input reference frequency also the main loop can control the output phase, independent from the output frequency, and reduce the lock-up time of the step frequency response. The experimental results confirm the validity of the proposed strategy.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.534-542
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• 2017

This paper presents a fast locking technique for a fractional-N PLL frequency synthesizer. The technique directly measures $K_{VCO}$ on a chip, computes the VCO's target tuning voltage for a given target frequency, and directly sets the loop filter voltage to the target voltage before the PLL begins the normal closed-loop locking process. The closed-loop lock time is significantly minimized because the initial frequency of the VCO are put very close to the desired final target value. The proposed technique is realized and designed for a 4.3-5.3 GHz fractional-N synthesizer in 65 nm CMOS and successfully verified through extensive simulations. The lock time is less than $12.8{\mu}s$ over the entire tuning range. Simulation verifications demonstrate that the proposed method is very effective in reducing the synthesizer lock time.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.37 no.3
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• pp.275-282
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• 2009

Generally, the sinusoidal cavity dither is adopted to ring laser gyroscope for eliminating the lock-in which is non-linear effect at the small rotation input. Despite this method, there are some remained errors which are generated at the dither turnaround, and those errors produce random walk which is a general character of a ring laser gyroscope. As one of the numerous research results for compensating these errors, there is a special lock-in compensation method which is the method of error estimation and compensation by comparing the beat signal periods of before and after the dither turnarounds. In this paper, by ring laser gyroscope modeling and numerical analysis, we verified the theoretical validity and confirmed the effectiveness of this method in expectation of the possible beat signal measurement time resolution. As a result, we confirmed the random walk decreases from a-half to a-third by this lock-in compensation method. So, it is expected to be a remarkable method for reducing the INS alignment time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.9
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• pp.1582-1589
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• 2006

A lock mechanism is essential for synchronization on the multiprocessor systems. The conventional queuing lock has two bus traffics that are the initial and retry of the lock-read. %is paper proposes the new locking protocol, called WPV (Waiting Processor Variable) lock mechanism, which has only one lock-read bus traffic command. The WPV mechanism accesses the shared data in the initial lock-read phase that is held in the pipelined protocol until the shared data is transferred. The nv mechanism also uses the cache state lock mechanism to reduce the locking overhead and guarantees the FIFO lock operations in the multiple lock contentions. In this paper, we also derive the analytical model of WPV lock mechanism as well as conventional memory and cache queuing lock mechanisms. The simulation results on the WPV lock mechanism show that about 50% of access time is reduced comparing with the conventional queuing lock mechanism.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1201-1204
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• 2003

This paper described a replica-delay adaptive lock-acquisition scheme for high-speed DLLs. The proposed scheme provides the fast and correct locking cycle that is variable according to the magnitude of the arbitrary replica delay (fixed delay). The scheme guarantees the wide operation range and the fast lock-aquisition time. It has been confirmed by HSPICE simulations in a 0.35${\mu}{\textrm}{m}$ CMOS process.