• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.3
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• pp.1-15
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• 1993

In this paper, we propose over-reporting avoidance scheme which avoids congestion of network traffics by adjusting managed system's over-reporting, on the OSI network management model which reports events from managed system to managing system. In case of reporting events from managed system to managing system, management traffic concentration occurs, and it causes over-loading on the managing system and congestion on the network. This scheme takes advantage of feedback from managing system to managed system. Managed system transmits event reports as much as maximum event pertime allocated to itself to managing system, and it sets it's management variables to LOCK state and stops event reports as Threshold time is reached. At the time, managing system directs event reports again by using M-set primitive with referring it's status. With this scheme, distributed processing, dynamic network adaptation, convergence of optimal operation point is possible. In addition to it, a fairness is assured. In order to detect characteristics of the Unary feedback over-reporting avoidance scheme. It is observed a control capability of the event reporting and fairness of each nodes through measuring. ThresholdTime value. It is measured a number of mean activating nodes and maintained time of LOCK state according to event reporting load, and also measured lost ratio of management packet, queuing delay in managing system, and goodput to observe effects of general packet load. Binary feedback scheme. Unary feedback overreporting avoidance scheme and raw scheme on the OSI network management system each are compared and analyzed, and finally proved that the scheme proposed in this study performs better.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.4
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• pp.470-476
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• 2019

The pattern locking technique applied to smart phones is a locking technique that many people use conveniently. However, the safety of pattern locking techniques is very low compared with other techniques. The pattern locking technique is vulnerable to a shoulder surfing attack, which is based on the user's input and can be interpreted by looking at the movement of the shoulder, and the smudge attack is also vulnerable due to fingerprint drag marks remaining on the mobile phone pad. Therefore, in this paper, we want to add a new security method to check the pressed time by using a thread in the pattern locking scheme to secure the vulnerability. It is divided into short, middle, and long click according to the pressing time at each point. When dragging using the technique, security performance enhances $3^n$ tiems. Therefore, even if dragging in the same 'ㄱ' manner, it becomes a completely different pattern depending on the pressing time at each point.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.189-189
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• 2010

The Improved flux-lock type superconducting fault current limiter(SFCL) is composed of a series transformer and superconducting unit of the YBCO coated conductor. The primary and secondary coils in the transformer were wound in series each other through an iron core and the YBCO coated conductor was connected with secondary coil in parallel. In a normal condition, the flux generated from a primary coil is cancelled out by its structure and the zero resistance of the YBCO thin films. When a fault occurs, the resistance of the YBCO coated conductor was generated and the fault current was limited by the SFCL. In this paper, we investigated the fault current limiting characteristics through the spot at the beginning of the fault current in the Improved flux-lock type SFCL. The experiment results that the fault current limiting characteristics was difference according to the point of a fault current started. Through the analysis, it was shown that shorter the time of a phase transition.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.408-420
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• 2003

This paper describes a Delay Locked Loop (DLL) circuit having two advancements : 1) a dual loop operation for a wide lock-range and 2) programmable replica delays using antifuse circuitry and internal voltage generator for a post-package skew calibration. The dual loop operation uses information from the initial time-difference between reference clock and internal clock to select one of the differential internal loops. This increases the lock-range of the DLL to the lower frequency. In addition, incorporation with the programmable replica delay using antifuse circuitry and internal voltage generator allows for the elimination of skews between external clock and internal clock that occur from on and off-chip variations after the package process. The proposed DLL, fabricated on 0.16m process, operates over the wide range of 42MHz - 400MHz with 2.3v power supply. The measured results show 43psec peak-to-peak jitter and 4.71psec ms jitter consuming 52㎽ at 400MHz.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.235-244
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• 2000

This paper presents a low power PLL based clock geneator circuit for microprocessors. It generates 32MHz${\sim}$1GHz clocks and can be integrated inside microprocessor chips. A high speed D Flip-Flop is designed using dynamic differential latch and a new Phase Frequency Detector(PFD) based on this FF is presented. The PFD enjoys low error characteristics in phase sensitivity and the PLL using this PFD has a low phase error. To improve the linearity of voltage controlled oscillator(VCO) in PLL, the voltage to current converter and current controlled oscillator combination is suggested. The resulting PLL provides wide lock range and extends frequency of generated clocks over 1 GHz. The clock generator is designed by using $0.65\;{\mu}m$ CMOS full custom technology and operates with $11\;{\mu}s$ lock-in time. The power consumption is less than 20mW.

• Journal of the Korean Institute of Intelligent Systems
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• v.25 no.6
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• pp.565-570
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• 2015

In this paper, we implemented the smart door lock system that control remotely devices using the concept of internet of things. Internet of things is intelligent system that can help devices to communicate with people and devices. And recently internet of things is getting attention because of advance of hardware technology and big data. The smart doorlock system based on internet of things used raspberry pi, sensor and doorlock. Using the smart phone, doorlock can be controlled from the raspberry pi server. And the user can identify some people that is in front of doorlock. also user can check around of doorlock in realtime using the raspberry pi camera.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.2
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• pp.13-18
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• 1984

The probability distribution of hold-in time and that of the time to reject false lock are investigated for the tracking procedure in spread spectrum communication systems. These are helpful in deciding dwell time and threshold level of correlatoi circuits. The probability distributions are derived by series expansion of generating function for discrete probability function and summation of the coefficients for corresponding terms. And the formulas described by general system parameters are obtained.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.6
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• pp.9-16
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• 2013

Bio-impedance measurement system(BMS) is non-invasive and easy to implement a measurement method that allows determining the water content of a patient. The measurement conditions, the hardware specifications and the configurations of BMS devices must be well chosen in order to get correct and reproducible results. BMS was then conducted for the limbs and the thoracic using a lock-in amplifier and LabView control system with a frequency range of 1kHz-100kHz. From both the measurement data and the simulation results, we verified that the parameters in the proposed equivalent model and the trend of impedance variation according to the multi-frequency of applied current source are similar to those of human body. We believe that the real-time BMS developed in this study is highly reliable and applicable to the research on the clinical characteristics of the human being's impedance.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.10
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• pp.1147-1158
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• 2008

In this paper, we designed a phase-looking circuit that locks the 16.8 GHz VTDRO to a 700 MHz SAW oscillator using SPD as a phase detector Direct phase locking with loop filter alone causes the problem of lock time, so VTDRO is phase leered by loop filter with the aid of time varying square wave current generator. The current generator is related to the loop filter and needs the systematic toning. In this paper, a systematic design of the current generator and loop filter is presented. The fabricated PLDRO shows a stabilized frequency of 16.8 GHz, a output power 6.3 dBm, and a phase noise of -101 dBc/Hz at the 100 kHz offset.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.2
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• pp.339-344
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• 2017

A novel structure of phase locked loop (PLL) which has small size and fast locking time with Early-late detector, Duty-rate modulator, and Lock status indicator (LSI) is proposed in this paper. The area of loop filter usually occupying the larger portion of the chip is minimized using a single small capacitor. While the conventional PLL with a single capacitor loop filter cannot work stably, the proposed PLL with two charge pumps works stably because the output voltage waveform of the proposed a single capacitor loop filter is the same as the output voltage waveform of the conventional 2nd-order loop filter. The two charge pumps are controlled by the Early-late detector which detects early-late status of UP and DN signals, and Duty-rate modulator which generates a steady duty-rate signal. Fast locking time is achieved using LSI. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.